SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 800742 | 1 | T4 | 188 | T5 | 36 | T6 | 8 | |||
auto[1] | 14217 | 1 | T25 | 80 | T26 | 80 | T42 | 392 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 814759 | 1 | T4 | 188 | T5 | 36 | T6 | 8 | |||
values[1] | 19 | 1 | T39 | 1 | T41 | 1 | T72 | 1 | |||
values[2] | 4 | 1 | T39 | 1 | T40 | 1 | T75 | 1 | |||
values[3] | 95 | 1 | T39 | 5 | T40 | 1 | T41 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 814779 | 1 | T4 | 188 | T5 | 36 | T6 | 8 | |||
values[1] | 21 | 1 | T39 | 1 | T41 | 2 | T75 | 2 | |||
values[2] | 12 | 1 | T39 | 1 | T41 | 1 | T120 | 1 | |||
values[3] | 88 | 1 | T39 | 3 | T40 | 7 | T41 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 814679 | 1 | T4 | 188 | T5 | 36 | T6 | 8 | |||
auto[TlIntgErrCmd] | 100 | 1 | T39 | 4 | T40 | 1 | T41 | 8 | |||
auto[TlIntgErrData] | 80 | 1 | T39 | 1 | T40 | 4 | T41 | 4 | |||
auto[TlIntgErrBoth] | 100 | 1 | T39 | 5 | T40 | 5 | T41 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 28715 | 0 | T2 | 12 | T31 | 8 | T35 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 28522 | 1 | T2 | 12 | T31 | 8 | T35 | 4 | |||
values[1] | 14 | 1 | T40 | 1 | T41 | 1 | T72 | 1 | |||
values[2] | 7 | 1 | T121 | 1 | T122 | 3 | T123 | 1 | |||
values[3] | 104 | 1 | T39 | 2 | T40 | 3 | T41 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 28540 | 1 | T2 | 12 | T31 | 8 | T35 | 4 | |||
values[1] | 10 | 1 | T40 | 1 | T41 | 1 | T75 | 1 | |||
values[2] | 3 | 1 | T120 | 1 | T124 | 1 | T122 | 1 | |||
values[3] | 92 | 1 | T39 | 4 | T40 | 3 | T41 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 28435 | 1 | T2 | 12 | T31 | 8 | T35 | 4 | |||
auto[TlIntgErrCmd] | 105 | 1 | T39 | 2 | T40 | 6 | T41 | 7 | |||
auto[TlIntgErrData] | 87 | 1 | T39 | 6 | T40 | 3 | T41 | 6 | |||
auto[TlIntgErrBoth] | 88 | 1 | T39 | 2 | T40 | 1 | T41 | 7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |