Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	246794	1		T4	102		T5	30		T6	4
full_word	568165	1		T4	86		T5	6		T6	4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	814679	1		T4	188		T5	36		T6	8
auto[TlIntgErrCmd]	100	1		T39	4		T40	1		T41	8
auto[TlIntgErrData]	80	1		T39	1		T40	4		T41	4
auto[TlIntgErrBoth]	100	1		T39	5		T40	5		T41	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	497343	1		T4	41		T7	9		T13	12
auto[1]	317616	1		T4	147		T5	36		T6	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	207271	1		T4	24		T7	6		T13	6
auto[TlIntgErrNone]	partial	auto[1]	39276	1		T4	78		T5	30		T6	4
auto[TlIntgErrNone]	full_word	auto[0]	289976	1		T4	17		T7	3		T13	6
auto[TlIntgErrNone]	full_word	auto[1]	278156	1		T4	69		T5	6		T6	4
auto[TlIntgErrCmd]	partial	auto[0]	30	1		T39	2		T41	3		T75	3
auto[TlIntgErrCmd]	partial	auto[1]	57	1		T39	1		T41	4		T72	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T40	1		T125	1		T126	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1		T39	1		T41	1		T72	1
auto[TlIntgErrData]	partial	auto[0]	31	1		T40	2		T72	5		T75	5
auto[TlIntgErrData]	partial	auto[1]	40	1		T39	1		T40	1		T41	4
auto[TlIntgErrData]	full_word	auto[0]	5	1		T40	1		T124	1		T127	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T75	1		T128	1		T129	1
auto[TlIntgErrBoth]	partial	auto[0]	23	1		T40	2		T41	2		T75	3
auto[TlIntgErrBoth]	partial	auto[1]	66	1		T39	5		T40	3		T41	6
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T129	2		T127	1		T126	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T72	3		T120	1		T130	2