Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	214566	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	567004	1		T4	86		T5	6		T6	4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	495900	1		T4	41		T7	9		T13	12
values[0x0]	140287	1		T4	74		T5	18		T6	3
values[0x1]	145383	1		T4	73		T5	18		T6	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	164355	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	617215	1		T4	98		T5	10		T6	4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2950	1		T23	8		T30	1		T133	1
valid_sources[0x01]	2821	1		T7	1		T26	1		T24	1
valid_sources[0x02]	2553	1		T7	3		T134	2		T135	1
valid_sources[0x03]	2931	1		T4	1		T24	3		T45	6
valid_sources[0x04]	2975	1		T4	4		T25	80		T24	1
valid_sources[0x05]	2670	1		T7	1		T26	2		T134	2
valid_sources[0x06]	2832	1		T13	2		T24	1		T133	7
valid_sources[0x07]	4711	1		T26	1		T136	1		T135	1
valid_sources[0x08]	3647	1		T134	1		T137	1		T45	15
valid_sources[0x09]	2756	1		T13	1		T24	1		T134	1
valid_sources[0x0a]	2529	1		T7	1		T134	1		T45	8
valid_sources[0x0b]	3048	1		T26	2		T138	1		T45	7
valid_sources[0x0c]	2833	1		T26	1		T45	5		T43	3
valid_sources[0x0d]	2410	1		T26	1		T139	5		T134	1
valid_sources[0x0e]	2838	1		T24	1		T45	13		T47	7
valid_sources[0x0f]	2602	1		T26	2		T138	1		T140	1
valid_sources[0x10]	5099	1		T4	2		T5	3		T134	1
valid_sources[0x11]	2598	1		T5	3		T134	1		T138	6
valid_sources[0x12]	2917	1		T24	1		T16	1		T134	1
valid_sources[0x13]	2955	1		T24	1		T134	1		T141	1
valid_sources[0x14]	3252	1		T26	1		T24	1		T45	7
valid_sources[0x15]	3042	1		T4	3		T24	1		T141	1
valid_sources[0x16]	2813	1		T26	1		T24	3		T16	1
valid_sources[0x17]	2981	1		T45	15		T46	6		T47	28
valid_sources[0x18]	2632	1		T15	67		T134	1		T140	1
valid_sources[0x19]	2637	1		T4	1		T141	1		T45	11
valid_sources[0x1a]	2808	1		T7	2		T138	1		T45	7
valid_sources[0x1b]	2492	1		T4	8		T26	1		T141	3
valid_sources[0x1c]	3129	1		T141	1		T142	1		T45	12
valid_sources[0x1d]	3052	1		T73	1		T14	3		T24	1
valid_sources[0x1e]	2874	1		T23	7		T24	2		T140	1
valid_sources[0x1f]	2594	1		T45	4		T47	2		T43	4
valid_sources[0x20]	2928	1		T45	8		T46	8		T47	5
valid_sources[0x21]	2872	1		T141	1		T135	2		T138	4
valid_sources[0x22]	2961	1		T13	3		T134	1		T143	2
valid_sources[0x23]	3575	1		T45	4		T46	8		T47	1
valid_sources[0x24]	2574	1		T24	1		T138	1		T140	1
valid_sources[0x25]	2714	1		T4	3		T26	1		T140	1
valid_sources[0x26]	2806	1		T26	1		T144	1		T45	9
valid_sources[0x27]	2985	1		T24	2		T134	1		T143	2
valid_sources[0x28]	2967	1		T24	2		T134	1		T143	1
valid_sources[0x29]	2704	1		T24	1		T140	3		T142	3
valid_sources[0x2a]	2988	1		T134	1		T135	1		T138	4
valid_sources[0x2b]	3106	1		T24	1		T134	1		T45	15
valid_sources[0x2c]	2942	1		T136	1		T141	2		T135	1
valid_sources[0x2d]	2634	1		T4	11		T6	1		T73	2
valid_sources[0x2e]	2556	1		T144	1		T134	1		T143	1
valid_sources[0x2f]	2935	1		T26	1		T24	2		T143	1
valid_sources[0x30]	2954	1		T13	2		T24	1		T140	3
valid_sources[0x31]	2550	1		T26	1		T24	1		T143	1
valid_sources[0x32]	2993	1		T13	1		T24	2		T134	1
valid_sources[0x33]	3161	1		T24	4		T141	4		T133	4
valid_sources[0x34]	2726	1		T141	3		T135	1		T142	1
valid_sources[0x35]	2807	1		T13	1		T138	1		T45	9
valid_sources[0x36]	3078	1		T135	1		T140	1		T45	5
valid_sources[0x37]	2668	1		T24	2		T141	1		T45	13
valid_sources[0x38]	2796	1		T4	4		T73	2		T15	50
valid_sources[0x39]	2694	1		T24	2		T142	1		T45	7
valid_sources[0x3a]	2928	1		T138	1		T45	16		T46	23
valid_sources[0x3b]	2846	1		T7	1		T26	1		T24	1
valid_sources[0x3c]	2943	1		T141	1		T142	1		T45	6
valid_sources[0x3d]	2770	1		T26	1		T24	1		T141	4
valid_sources[0x3e]	2626	1		T13	1		T134	2		T45	11
valid_sources[0x3f]	2759	1		T138	6		T45	13		T46	25
valid_sources[0x40]	2918	1		T7	1		T24	3		T143	1
valid_sources[0x41]	2824	1		T4	2		T24	1		T141	2
valid_sources[0x42]	3432	1		T24	1		T133	2		T138	3
valid_sources[0x43]	2370	1		T14	8		T45	4		T46	18
valid_sources[0x44]	2550	1		T134	1		T138	2		T140	1
valid_sources[0x45]	2578	1		T16	2		T134	1		T141	2
valid_sources[0x46]	2835	1		T133	1		T140	2		T45	27
valid_sources[0x47]	4106	1		T7	1		T24	2		T134	1
valid_sources[0x48]	2739	1		T4	3		T9	40		T133	2
valid_sources[0x49]	2765	1		T7	2		T23	1		T20	1
valid_sources[0x4a]	2721	1		T141	1		T143	1		T133	2
valid_sources[0x4b]	3320	1		T4	1		T24	1		T134	1
valid_sources[0x4c]	2622	1		T24	1		T134	1		T133	7
valid_sources[0x4d]	2911	1		T14	7		T24	1		T134	1
valid_sources[0x4e]	3094	1		T24	1		T138	1		T142	1
valid_sources[0x4f]	2674	1		T4	5		T26	1		T141	1
valid_sources[0x50]	2978	1		T26	1		T24	1		T134	2
valid_sources[0x51]	2552	1		T24	1		T143	5		T138	1
valid_sources[0x52]	2809	1		T24	1		T134	1		T143	4
valid_sources[0x53]	2682	1		T5	5		T7	2		T134	1
valid_sources[0x54]	3121	1		T4	1		T5	1		T134	1
valid_sources[0x55]	2945	1		T4	2		T26	1		T24	3
valid_sources[0x56]	2927	1		T45	17		T47	2		T55	2
valid_sources[0x57]	2820	1		T6	2		T7	3		T26	1
valid_sources[0x58]	2750	1		T73	2		T26	1		T24	1
valid_sources[0x59]	3066	1		T24	1		T134	1		T45	7
valid_sources[0x5a]	3403	1		T24	1		T134	1		T143	2
valid_sources[0x5b]	3221	1		T5	7		T24	2		T134	2
valid_sources[0x5c]	3272	1		T24	3		T134	1		T141	1
valid_sources[0x5d]	2763	1		T134	1		T141	1		T140	1
valid_sources[0x5e]	3425	1		T26	1		T141	1		T142	2
valid_sources[0x5f]	3109	1		T10	37		T13	1		T24	1
valid_sources[0x60]	2600	1		T14	2		T24	1		T141	3
valid_sources[0x61]	3210	1		T24	2		T138	1		T45	10
valid_sources[0x62]	2483	1		T24	3		T45	3		T47	2
valid_sources[0x63]	2648	1		T13	2		T24	1		T144	1
valid_sources[0x64]	2767	1		T26	2		T14	3		T144	2
valid_sources[0x65]	2223	1		T4	5		T26	2		T144	2
valid_sources[0x66]	2559	1		T45	6		T43	2		T55	1
valid_sources[0x67]	2843	1		T26	1		T24	1		T134	1
valid_sources[0x68]	3080	1		T7	2		T26	1		T24	1
valid_sources[0x69]	3478	1		T24	1		T134	2		T141	1
valid_sources[0x6a]	2451	1		T26	1		T24	1		T45	27
valid_sources[0x6b]	2623	1		T134	1		T138	3		T45	20
valid_sources[0x6c]	2797	1		T24	2		T134	2		T143	1
valid_sources[0x6d]	2967	1		T24	1		T144	1		T134	2
valid_sources[0x6e]	2669	1		T145	1		T24	2		T134	1
valid_sources[0x6f]	3037	1		T26	1		T24	1		T134	1
valid_sources[0x70]	2844	1		T24	2		T142	1		T45	12
valid_sources[0x71]	2941	1		T26	1		T24	2		T134	1
valid_sources[0x72]	2767	1		T45	8		T46	10		T42	2
valid_sources[0x73]	2916	1		T24	1		T134	3		T141	1
valid_sources[0x74]	3226	1		T141	1		T143	1		T138	3
valid_sources[0x75]	2156	1		T24	2		T45	4		T42	10
valid_sources[0x76]	2928	1		T4	3		T13	2		T138	1
valid_sources[0x77]	2868	1		T24	2		T45	7		T47	11
valid_sources[0x78]	2716	1		T4	8		T138	2		T142	2
valid_sources[0x79]	2707	1		T24	3		T134	2		T141	2
valid_sources[0x7a]	2775	1		T24	3		T134	2		T140	1
valid_sources[0x7b]	2811	1		T26	1		T24	1		T45	13
valid_sources[0x7c]	2792	1		T7	1		T26	1		T134	3
valid_sources[0x7d]	3167	1		T15	41		T24	1		T134	1
valid_sources[0x7e]	2906	1		T24	1		T141	1		T138	1
valid_sources[0x7f]	3134	1		T4	4		T134	1		T141	1
valid_sources[0x80]	2948	1		T24	1		T134	1		T138	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

289846

1

T4

17

T7

3

T13

6

values[0x0]

all_enables

biggest_size

138273

1

T4

37

T5

3

T6

3

values[0x1]

all_enables

biggest_size

138885

1

T4

32

T5

3

T6

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2188	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	16337	1		T2	4		T31	1		T35	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5635	1		T45	8		T46	6		T42	12
values[0x0]	6439	1		T2	6		T31	4		T35	1
values[0x1]	6451	1		T2	6		T31	4		T35	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1688	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	16837	1		T2	4		T31	3		T35	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	115	1		T31	8		T74	6		T41	1
valid_sources[0x01]	52	1		T42	1		T43	2		T55	3
valid_sources[0x02]	43	1		T74	3		T76	7		T83	2
valid_sources[0x03]	157	1		T42	1		T55	4		T74	2
valid_sources[0x04]	103	1		T42	1		T44	1		T83	1
valid_sources[0x05]	57	1		T55	7		T76	2		T77	2
valid_sources[0x06]	50	1		T41	1		T146	2		T110	5
valid_sources[0x07]	49	1		T74	3		T72	1		T77	3
valid_sources[0x08]	90	1		T147	1		T148	3		T56	5
valid_sources[0x09]	82	1		T149	2		T42	1		T41	1
valid_sources[0x0a]	58	1		T2	1		T150	1		T74	1
valid_sources[0x0b]	69	1		T151	1		T74	3		T44	1
valid_sources[0x0c]	74	1		T49	1		T61	27		T77	4
valid_sources[0x0d]	33	1		T152	2		T74	1		T80	2
valid_sources[0x0e]	117	1		T49	1		T74	2		T77	2
valid_sources[0x0f]	39	1		T43	1		T77	1		T83	1
valid_sources[0x10]	71	1		T2	1		T115	3		T76	15
valid_sources[0x11]	42	1		T55	3		T40	1		T146	2
valid_sources[0x12]	53	1		T151	1		T46	1		T47	1
valid_sources[0x13]	40	1		T55	6		T74	1		T83	1
valid_sources[0x14]	47	1		T74	1		T56	1		T41	2
valid_sources[0x15]	46	1		T153	1		T74	1		T44	1
valid_sources[0x16]	332	1		T154	2		T55	3		T74	2
valid_sources[0x17]	49	1		T42	1		T41	1		T83	3
valid_sources[0x18]	43	1		T50	1		T44	1		T72	1
valid_sources[0x19]	55	1		T74	2		T40	1		T41	1
valid_sources[0x1a]	91	1		T43	1		T55	1		T44	2
valid_sources[0x1b]	118	1		T55	6		T77	1		T83	3
valid_sources[0x1c]	36	1		T45	8		T55	4		T56	2
valid_sources[0x1d]	190	1		T47	1		T74	1		T76	1
valid_sources[0x1e]	73	1		T51	1		T78	1		T55	2
valid_sources[0x1f]	223	1		T155	1		T74	1		T56	1
valid_sources[0x20]	42	1		T153	1		T55	1		T80	2
valid_sources[0x21]	235	1		T156	1		T157	1		T74	7
valid_sources[0x22]	54	1		T74	2		T44	1		T83	1
valid_sources[0x23]	80	1		T158	16		T55	3		T72	1
valid_sources[0x24]	80	1		T49	1		T159	7		T42	1
valid_sources[0x25]	56	1		T114	1		T74	4		T56	1
valid_sources[0x26]	46	1		T51	1		T74	4		T80	1
valid_sources[0x27]	179	1		T116	3		T55	1		T74	2
valid_sources[0x28]	129	1		T42	2		T56	1		T44	1
valid_sources[0x29]	42	1		T74	2		T56	5		T80	1
valid_sources[0x2a]	59	1		T47	1		T74	1		T83	3
valid_sources[0x2b]	56	1		T55	6		T56	1		T44	1
valid_sources[0x2c]	126	1		T114	1		T74	3		T40	1
valid_sources[0x2d]	75	1		T51	4		T151	1		T42	1
valid_sources[0x2e]	42	1		T78	1		T114	1		T155	1
valid_sources[0x2f]	42	1		T74	1		T72	1		T77	2
valid_sources[0x30]	39	1		T155	1		T74	1		T83	1
valid_sources[0x31]	47	1		T147	1		T42	1		T55	7
valid_sources[0x32]	52	1		T49	1		T42	1		T55	4
valid_sources[0x33]	30	1		T2	1		T77	1		T83	2
valid_sources[0x34]	95	1		T74	2		T56	1		T41	1
valid_sources[0x35]	62	1		T55	7		T74	1		T56	2
valid_sources[0x36]	104	1		T2	1		T74	2		T44	1
valid_sources[0x37]	42	1		T55	5		T74	4		T44	2
valid_sources[0x38]	61	1		T156	1		T55	5		T74	1
valid_sources[0x39]	52	1		T42	1		T74	3		T77	2
valid_sources[0x3a]	81	1		T54	1		T41	1		T77	2
valid_sources[0x3b]	133	1		T49	1		T43	1		T56	1
valid_sources[0x3c]	58	1		T74	3		T44	1		T83	2
valid_sources[0x3d]	33	1		T42	1		T44	1		T77	1
valid_sources[0x3e]	50	1		T78	1		T74	2		T44	1
valid_sources[0x3f]	50	1		T43	1		T74	1		T72	1
valid_sources[0x40]	108	1		T55	2		T74	2		T41	1
valid_sources[0x41]	83	1		T42	1		T55	3		T74	2
valid_sources[0x42]	74	1		T54	1		T147	1		T46	1
valid_sources[0x43]	27	1		T43	1		T74	5		T41	1
valid_sources[0x44]	106	1		T150	1		T74	1		T40	1
valid_sources[0x45]	159	1		T49	1		T55	2		T74	2
valid_sources[0x46]	70	1		T43	2		T74	3		T56	1
valid_sources[0x47]	42	1		T55	2		T74	1		T56	6
valid_sources[0x48]	61	1		T43	1		T83	1		T106	1
valid_sources[0x49]	235	1		T48	1		T74	1		T41	1
valid_sources[0x4a]	50	1		T74	2		T41	1		T146	1
valid_sources[0x4b]	55	1		T147	1		T55	1		T74	1
valid_sources[0x4c]	72	1		T49	1		T42	1		T74	2
valid_sources[0x4d]	191	1		T77	2		T83	1		T146	2
valid_sources[0x4e]	55	1		T43	1		T55	2		T77	4
valid_sources[0x4f]	117	1		T46	1		T74	1		T44	1
valid_sources[0x50]	109	1		T78	1		T148	2		T46	1
valid_sources[0x51]	51	1		T74	1		T44	1		T77	1
valid_sources[0x52]	44	1		T51	1		T74	1		T40	1
valid_sources[0x53]	56	1		T2	1		T152	1		T155	1
valid_sources[0x54]	61	1		T56	1		T44	1		T41	2
valid_sources[0x55]	153	1		T49	1		T160	11		T161	2
valid_sources[0x56]	70	1		T55	2		T74	1		T131	6
valid_sources[0x57]	74	1		T2	1		T51	1		T150	1
valid_sources[0x58]	79	1		T152	1		T153	1		T43	1
valid_sources[0x59]	31	1		T78	1		T74	2		T80	1
valid_sources[0x5a]	50	1		T74	2		T83	1		T146	3
valid_sources[0x5b]	62	1		T46	1		T42	1		T55	7
valid_sources[0x5c]	130	1		T49	1		T156	1		T74	3
valid_sources[0x5d]	46	1		T42	1		T74	1		T56	2
valid_sources[0x5e]	122	1		T162	10		T55	5		T74	1
valid_sources[0x5f]	61	1		T55	4		T56	7		T146	2
valid_sources[0x60]	58	1		T114	2		T46	1		T43	1
valid_sources[0x61]	95	1		T56	3		T76	4		T77	3
valid_sources[0x62]	112	1		T114	1		T74	2		T44	1
valid_sources[0x63]	56	1		T55	7		T80	1		T76	4
valid_sources[0x64]	48	1		T114	1		T74	1		T44	1
valid_sources[0x65]	128	1		T74	2		T146	1		T163	1
valid_sources[0x66]	62	1		T74	1		T56	1		T44	2
valid_sources[0x67]	52	1		T78	1		T147	1		T74	1
valid_sources[0x68]	62	1		T43	1		T55	4		T74	3
valid_sources[0x69]	55	1		T164	10		T42	1		T56	2
valid_sources[0x6a]	32	1		T152	1		T55	4		T74	2
valid_sources[0x6b]	85	1		T42	1		T47	1		T43	1
valid_sources[0x6c]	34	1		T155	4		T42	3		T74	1
valid_sources[0x6d]	119	1		T55	11		T74	1		T83	2
valid_sources[0x6e]	52	1		T148	3		T42	1		T55	4
valid_sources[0x6f]	61	1		T49	1		T54	1		T74	4
valid_sources[0x70]	65	1		T149	2		T55	19		T74	1
valid_sources[0x71]	50	1		T43	2		T55	1		T74	2
valid_sources[0x72]	58	1		T78	1		T155	4		T44	1
valid_sources[0x73]	39	1		T49	1		T77	1		T83	1
valid_sources[0x74]	101	1		T159	3		T74	2		T163	1
valid_sources[0x75]	53	1		T155	3		T46	1		T44	2
valid_sources[0x76]	55	1		T35	4		T147	1		T165	1
valid_sources[0x77]	40	1		T2	1		T166	1		T43	3
valid_sources[0x78]	45	1		T78	1		T167	1		T74	2
valid_sources[0x79]	40	1		T49	1		T43	1		T74	1
valid_sources[0x7a]	79	1		T168	2		T151	1		T74	4
valid_sources[0x7b]	40	1		T49	1		T169	7		T43	1
valid_sources[0x7c]	273	1		T51	1		T78	1		T55	4
valid_sources[0x7d]	66	1		T48	1		T54	1		T169	1
valid_sources[0x7e]	99	1		T114	1		T42	2		T74	4
valid_sources[0x7f]	37	1		T74	1		T41	1		T72	1
valid_sources[0x80]	40	1		T74	1		T83	1		T120	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4575

1

T45

8

T46

6

T42

12

values[0x0]

all_enables

biggest_size

5979

1

T2

2

T31

1

T35

1

values[0x1]

all_enables

biggest_size

5783

1

T2

2

T49

3

T54

1