Module Definition
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Module : dm_csrs
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.17 85.35 61.33 57.83

Source File(s) :
/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_csrs.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_dm_top.i_dm_csrs 68.17 85.35 61.33 57.83



Module Instance : tb.dut.u_dm_top.i_dm_csrs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.17 85.35 61.33 57.83


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.74 87.22 63.37 64.36 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_dm_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
i_fifo 90.92 100.00 69.23 94.44 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : dm_csrs
Line No.TotalCoveredPercent
TOTAL27323385.35
CONT_ASSIGN8811100.00
ALWAYS10677100.00
ALWAYS11988100.00
ALWAYS13688100.00
ALWAYS15244100.00
CONT_ASSIGN18111100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18511100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN19911100.00
ALWAYS203200.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21711100.00
ALWAYS22417013277.65
ALWAYS56066100.00
CONT_ASSIGN57011100.00
CONT_ASSIGN57111100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57311100.00
CONT_ASSIGN57411100.00
CONT_ASSIGN57611100.00
CONT_ASSIGN57911100.00
ALWAYS6034646100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_csrs.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_csrs.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
106 1 1
107 1 1
108 1 1
109 1 1
110 1 1
111 1 1
112 1 1
==> MISSING_ELSE
119 1 1
120 1 1
121 1 1
123 1 1
124 1 1
126 1 1
128 1 1
129 1 1
==> MISSING_ELSE
136 1 1
137 1 1
138 1 1
140 1 1
141 1 1
143 1 1
145 1 1
146 1 1
==> MISSING_ELSE
152 1 1
153 1 1
154 1 1
156 1 1
181 1 1
182 1 1
183 1 1
184 1 1
185 1 1
186 1 1
188 1 1
194 1 1
195 1 1
196 1 1
198 1 1
199 1 1
203 0 1
204 0 1
214 1 1
217 1 1
224 1 1
225 1 1
227 1 1
229 1 1
231 1 1
232 1 1
234 1 1
235 1 1
237 1 1
238 1 1
242 1 1
243 1 1
247 1 1
248 1 1
250 1 1
251 1 1
254 1 1
255 1 1
256 1 1
257 1 1
258 1 1
261 1 1
262 1 1
265 1 1
266 1 1
267 1 1
268 1 1
269 1 1
270 1 1
271 1 1
272 1 1
273 1 1
275 1 1
276 1 1
277 1 1
278 1 1
279 1 1
280 1 1
281 1 1
284 1 1
285 1 1
288 1 1
289 1 1
291 1 1
292 1 1
294 1 1
297 1 1
298 1 1
299 0 1
MISSING_ELSE
303 1 1
304 1 1
305 0 1
306 1 1
307 0 1
309 0 1
311 1 1
312 1 1
315 1 1
319 1 1
320 1 1
321 0 1
MISSING_ELSE
325 0 1
326 0 1
327 0 1
328 0 1
330 1 1
333 1 1
336 0 1
340 1 1
341 0 1
342 0 1
344 1 1
345 1 1
350 0 1
351 0 1
352 0 1
354 0 1
MISSING_ELSE
362 1 1
363 1 1
365 1 1
367 1 1
368 1 1
370 1 1
373 1 1
374 1 1
375 0 1
MISSING_ELSE
==> MISSING_ELSE
381 1 1
383 1 1
384 0 1
MISSING_ELSE
387 0 1
388 0 1
395 1 1
397 1 1
398 0 1
400 1 1
401 1 1
402 0 1
MISSING_ELSE
408 1 1
409 1 1
410 1 1
414 1 1
415 1 1
416 0 1
MISSING_ELSE
422 1 1
423 1 1
424 1 1
425 1 1
427 1 1
428 1 1
429 0 1
MISSING_ELSE
435 1 1
436 1 1
441 1 1
444 1 1
445 1 1
446 1 1
MISSING_ELSE
452 1 1
453 0 1
454 0 1
456 1 1
457 1 1
459 1 1
460 1 1
465 1 1
466 0 1
467 0 1
469 1 1
470 1 1
475 0 1
476 0 1
477 0 1
479 0 1
484 1 1
485 0 1
486 0 1
488 1 1
489 1 1
494 0 1
495 0 1
496 0 1
498 0 1
MISSING_ELSE
505 1 1
506 1 1
MISSING_ELSE
510 1 1
511 1 1
MISSING_ELSE
515 1 1
516 1 1
MISSING_ELSE
522 1 1
523 1 1
MISSING_ELSE
526 1 1
527 1 1
MISSING_ELSE
532 1 1
534 1 1
535 1 1
536 1 1
537 1 1
538 1 1
540 1 1
541 1 1
542 1 1
MISSING_ELSE
544 1 1
545 1 1
MISSING_ELSE
548 1 1
549 1 1
550 1 1
551 1 1
552 1 1
553 1 1
554 1 1
555 1 1
560 1 1
562 1 1
563 1 1
564 1 1
565 1 1
566 1 1
==> MISSING_ELSE
570 1 1
571 1 1
572 1 1
573 1 1
574 1 1
576 1 1
579 1 1
603 1 1
604 1 1
606 1 1
607 1 1
608 1 1
609 1 1
610 1 1
611 1 1
612 1 1
613 1 1
614 1 1
615 1 1
617 1 1
619 1 1
620 1 1
621 1 1
622 1 1
623 1 1
624 1 1
625 1 1
626 1 1
627 1 1
628 1 1
629 1 1
630 1 1
631 1 1
633 1 1
634 1 1
635 1 1
636 1 1
637 1 1
638 1 1
639 1 1
640 1 1
641 1 1
642 1 1
644 1 1
645 1 1
646 1 1
647 1 1
648 1 1
649 1 1
650 1 1
651 1 1
652 1 1
653 1 1


Cond Coverage for Module : dm_csrs
TotalCoveredPercent
Conditions754661.33
Logical754661.33
Non-Logical00
Event00

 LINE       247
 EXPRESSION (halted_aligned[selected_hart] & ((~unavailable_aligned[selected_hart])))
             --------------1--------------   -------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT4,T5,T7

 LINE       248
 EXPRESSION (halted_aligned[selected_hart] & ((~unavailable_aligned[selected_hart])))
             --------------1--------------   -------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT4,T5,T7

 LINE       250
 EXPRESSION (((~halted_aligned[selected_hart])) & ((~unavailable_aligned[selected_hart])))
             -----------------1----------------   -------------------2-------------------
-1--2-StatusTests
01CoveredT4,T5,T7
10CoveredT4,T8,T5
11CoveredT1,T2,T3

 LINE       251
 EXPRESSION (((~halted_aligned[selected_hart])) & ((~unavailable_aligned[selected_hart])))
             -----------------1----------------   -------------------2-------------------
-1--2-StatusTests
01CoveredT4,T5,T7
10CoveredT4,T8,T5
11CoveredT1,T2,T3

 LINE       288
 EXPRESSION (dmi_req_ready_o && dmi_req_valid_i && (dtm_op == DTM_READ))
             -------1-------    -------2-------    ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T4
110CoveredT1,T2,T3
111CoveredT1,T3,T4

 LINE       288
 SUB-EXPRESSION (dtm_op == DTM_READ)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       298
 EXPRESSION (cmderr_q == CmdErrNone)
            ------------1-----------
-1-StatusTests
0CoveredT4,T9,T10
1Not Covered

 LINE       320
 EXPRESSION (cmderr_q == CmdErrNone)
            ------------1-----------
-1-StatusTests
0CoveredT4,T9,T10
1Not Covered

 LINE       340
 EXPRESSION (sbbusy_i || sbcs_q.sbbusyerror)
             ----1---    ---------2--------
-1--2-StatusTests
00CoveredT1,T3,T11
01Not Covered
10Not Covered

 LINE       344
 EXPRESSION (sbcs_q.sberror == '0)
            -----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T3,T11

 LINE       350
 EXPRESSION (sbbusy_i || sbcs_q.sbbusyerror)
             ----1---    ---------2--------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       362
 EXPRESSION (dmi_req_ready_o && dmi_req_valid_i && (dtm_op == DTM_WRITE))
             -------1-------    -------2-------    ----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT1,T3,T4
111CoveredT1,T2,T3

 LINE       362
 SUB-EXPRESSION (dtm_op == DTM_WRITE)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       374
 EXPRESSION (cmderr_q == CmdErrNone)
            ------------1-----------
-1-StatusTests
0CoveredT4,T9,T10
1Not Covered

 LINE       401
 EXPRESSION (cmderr_q == CmdErrNone)
            ------------1-----------
-1-StatusTests
0CoveredT4,T9,T10
1Not Covered

 LINE       415
 EXPRESSION (cmderr_q == CmdErrNone)
            ------------1-----------
-1-StatusTests
0CoveredT4,T6,T9
1Not Covered

 LINE       428
 EXPRESSION (cmderr_q == CmdErrNone)
            ------------1-----------
-1-StatusTests
0CoveredT4,T9,T10
1Not Covered

 LINE       445
 EXPRESSION (cmderr_q == CmdErrNone)
            ------------1-----------
-1-StatusTests
0CoveredT4,T9,T10
1CoveredT4,T9,T10

 LINE       459
 EXPRESSION (sbcs_q.sbbusyerror & ((~sbcs.sbbusyerror)))
             ---------1--------   ----------2----------
-1--2-StatusTests
01CoveredT1,T3,T11
10Not Covered
11Not Covered

 LINE       460
 EXPRESSION (((|sbcs.sberror)) ? 3'b0 : sbcs_q.sberror)
             --------1--------
-1-StatusTests
0CoveredT1,T3,T11
1CoveredT1,T11,T12

 LINE       465
 EXPRESSION (sbbusy_i || sbcs_q.sbbusyerror)
             ----1---    ---------2--------
-1--2-StatusTests
00CoveredT1,T3,T11
01Not Covered
10Not Covered

 LINE       470
 EXPRESSION (sbcs_q.sberror == '0)
            -----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T3,T11

 LINE       475
 EXPRESSION (sbbusy_i || sbcs_q.sbbusyerror)
             ----1---    ---------2--------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       484
 EXPRESSION (sbbusy_i || sbcs_q.sbbusyerror)
             ----1---    ---------2--------
-1--2-StatusTests
00CoveredT1,T3,T11
01Not Covered
10Not Covered

 LINE       489
 EXPRESSION (sbcs_q.sberror == '0)
            -----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T3,T11

 LINE       494
 EXPRESSION (sbbusy_i || sbcs_q.sbbusyerror)
             ----1---    ---------2--------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       541
 EXPRESSION (((!dmcontrol_q.resumereq)) && dmcontrol_d.resumereq)
             -------------1------------    ----------2----------
-1--2-StatusTests
01CoveredT4,T7,T13
10CoveredT1,T2,T3
11CoveredT4,T7,T13

 LINE       544
 EXPRESSION (dmcontrol_q.resumereq && resumeack_i)
             ----------1----------    -----2-----
-1--2-StatusTests
01CoveredT4,T7,T13
10CoveredT4,T7,T13
11CoveredT4,T7,T13

 LINE       617
 EXPRESSION (SelectableHarts & havereset_d)
             -------1-------   -----2-----
-1--2-StatusTests
-0Not Covered
-1CoveredT1,T2,T3

Branch Coverage for Module : dm_csrs
Line No.TotalCoveredPercent
Branches 83 48 57.83
IF 111 2 1 50.00
IF 128 2 1 50.00
IF 145 2 1 50.00
IF 288 25 11 44.00
IF 362 33 16 48.48
IF 505 2 2 100.00
IF 510 2 2 100.00
IF 515 2 2 100.00
IF 522 2 2 100.00
IF 526 2 2 100.00
IF 541 2 2 100.00
IF 544 2 2 100.00
IF 564 2 1 50.00
IF 603 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_csrs.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_csrs.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 111 if ((hartsel_idx0 < 15'((((NrHarts - 1) / (2 ** 5)) + 1))))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 128 if ((hartsel_idx1 < 10'((((NrHarts - 1) / (2 ** 10)) + 1))))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 145 if ((hartsel_idx2 < 5'((((NrHarts - 1) / (2 ** 15)) + 1))))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 288 if (((dmi_req_ready_o && dmi_req_valid_i) && (dtm_op == DTM_READ))) -2-: 289 case (dm_csr_addr) -3-: 292 if ((!cmdbusy_i)) -4-: 298 if ((cmderr_q == CmdErrNone)) -5-: 312 if ((!cmdbusy_i)) -6-: 320 if ((cmderr_q == CmdErrNone)) -7-: 340 if ((sbbusy_i || sbcs_q.sbbusyerror)) -8-: 350 if ((sbbusy_i || sbcs_q.sbbusyerror))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
1 Data0 DataEnd 1 - - - - - Covered T5,T7,T14
1 Data0 DataEnd 0 1 - - - - Not Covered
1 Data0 DataEnd 0 0 - - - - Covered T4,T9,T10
1 DMControl - - - - - - Covered T4,T15,T16
1 DMStatus - - - - - - Covered T4,T8,T5
1 Hartinfo - - - - - - Not Covered
1 AbstractCS - - - - - - Covered T4,T5,T6
1 AbstractAuto - - - - - - Not Covered
1 Command - - - - - - Not Covered
1 ProgBuf0 ProgBufEnd - - 1 - - - Covered T4,T5,T7
1 ProgBuf0 ProgBufEnd - - 0 1 - - Not Covered
1 ProgBuf0 ProgBufEnd - - 0 0 - - Covered T4,T9,T10
1 HaltSum0 - - - - - - Not Covered
1 HaltSum1 - - - - - - Not Covered
1 HaltSum2 - - - - - - Not Covered
1 HaltSum3 - - - - - - Not Covered
1 SBCS - - - - - - Covered T1,T3,T11
1 SBAddress0 - - - - - - Covered T1,T17,T18
1 SBAddress1 - - - - - - Not Covered
1 SBData0 - - - - 1 - Not Covered
1 SBData0 - - - - 0 - Covered T1,T3,T11
1 SBData1 - - - - - 1 Not Covered
1 SBData1 - - - - - 0 Not Covered
1 default - - - - - - Not Covered
0 - - - - - - - Covered T1,T2,T3


LineNo. Expression -1-: 362 if (((dmi_req_ready_o && dmi_req_valid_i) && (dtm_op == DTM_WRITE))) -2-: 363 case (dm_csr_addr) -3-: 365 if ((dm::DataCount > 4'b0)) -4-: 367 if ((!cmdbusy_i)) -5-: 374 if ((cmderr_q == CmdErrNone)) -6-: 383 if (dmcontrol_d.ackhavereset) -7-: 397 if ((!cmdbusy_i)) -8-: 401 if ((cmderr_q == CmdErrNone)) -9-: 408 if ((!cmdbusy_i)) -10-: 415 if ((cmderr_q == CmdErrNone)) -11-: 422 if ((!cmdbusy_i)) -12-: 428 if ((cmderr_q == CmdErrNone)) -13-: 435 if ((!cmdbusy_i)) -14-: 445 if ((cmderr_q == CmdErrNone)) -15-: 452 if (sbbusy_i) -16-: 460 ((|sbcs.sberror)) ? -17-: 465 if ((sbbusy_i || sbcs_q.sbbusyerror)) -18-: 475 if ((sbbusy_i || sbcs_q.sbbusyerror)) -19-: 484 if ((sbbusy_i || sbcs_q.sbbusyerror)) -20-: 494 if ((sbbusy_i || sbcs_q.sbbusyerror))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20-StatusTests
1 Data0 DataEnd 1 1 - - - - - - - - - - - - - - - - Covered T19,T5,T7
1 Data0 DataEnd 1 0 1 - - - - - - - - - - - - - - - Not Covered
1 Data0 DataEnd 1 0 0 - - - - - - - - - - - - - - - Covered T4,T9,T10
1 Data0 DataEnd 0 - - - - - - - - - - - - - - - - - Not Covered
1 DMControl - - - 1 - - - - - - - - - - - - - - Not Covered
1 DMControl - - - 0 - - - - - - - - - - - - - - Covered T1,T2,T3
1 DMStatus - - - - - - - - - - - - - - - - - - Not Covered
1 Hartinfo - - - - - - - - - - - - - - - - - - Not Covered
1 AbstractCS - - - - 1 - - - - - - - - - - - - - Not Covered
1 AbstractCS - - - - 0 1 - - - - - - - - - - - - Not Covered
1 AbstractCS - - - - 0 0 - - - - - - - - - - - - Covered T4,T9,T10
1 Command - - - - - - 1 - - - - - - - - - - - Covered T4,T19,T5
1 Command - - - - - - 0 1 - - - - - - - - - - Not Covered
1 Command - - - - - - 0 0 - - - - - - - - - - Covered T4,T6,T9
1 AbstractAuto - - - - - - - - 1 - - - - - - - - - Covered T4,T5,T7
1 AbstractAuto - - - - - - - - 0 1 - - - - - - - - Not Covered
1 AbstractAuto - - - - - - - - 0 0 - - - - - - - - Covered T4,T9,T10
1 ProgBuf0 ProgBufEnd - - - - - - - - - - 1 - - - - - - - Covered T4,T19,T5
1 ProgBuf0 ProgBufEnd - - - - - - - - - - 0 1 - - - - - - Covered T4,T9,T10
1 ProgBuf0 ProgBufEnd - - - - - - - - - - 0 0 - - - - - - Covered T4,T9,T10
1 SBCS - - - - - - - - - - - - 1 - - - - - Not Covered
1 SBCS - - - - - - - - - - - - 0 1 - - - - Covered T1,T11,T12
1 SBCS - - - - - - - - - - - - 0 0 - - - - Covered T1,T3,T11
1 SBAddress0 - - - - - - - - - - - - - - 1 - - - Not Covered
1 SBAddress0 - - - - - - - - - - - - - - 0 - - - Covered T1,T3,T11
1 SBAddress1 - - - - - - - - - - - - - - - 1 - - Not Covered
1 SBAddress1 - - - - - - - - - - - - - - - 0 - - Not Covered
1 SBData0 - - - - - - - - - - - - - - - - 1 - Not Covered
1 SBData0 - - - - - - - - - - - - - - - - 0 - Covered T1,T3,T11
1 SBData1 - - - - - - - - - - - - - - - - - 1 Not Covered
1 SBData1 - - - - - - - - - - - - - - - - - 0 Not Covered
1 default - - - - - - - - - - - - - - - - - - Not Covered
0 - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3


LineNo. Expression -1-: 505 if (cmderror_valid_i)

Branches:
-1-StatusTests
1 Covered T4,T19,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 510 if (data_valid_i)

Branches:
-1-StatusTests
1 Covered T4,T20,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 515 if (ndmreset_o)

Branches:
-1-StatusTests
1 Covered T4,T8,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 522 if (sberror_valid_i)

Branches:
-1-StatusTests
1 Covered T1,T11,T12
0 Covered T1,T2,T3


LineNo. Expression -1-: 526 if (sbdata_valid_i)

Branches:
-1-StatusTests
1 Covered T1,T3,T11
0 Covered T1,T2,T3


LineNo. Expression -1-: 541 if (((!dmcontrol_q.resumereq) && dmcontrol_d.resumereq))

Branches:
-1-StatusTests
1 Covered T4,T7,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 544 if ((dmcontrol_q.resumereq && resumeack_i))

Branches:
-1-StatusTests
1 Covered T4,T7,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 564 if ((selected_hart <= 1'((NrHarts - 1))))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 603 if ((!rst_ni)) -2-: 619 if ((!dmcontrol_q.dmactive))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%