Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.77 92.87 79.06 89.36 76.92 83.07 97.75 95.34


Total test records in report: 372
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html
T273 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3779136096 Mar 10 01:13:19 PM PDT 24 Mar 10 01:13:22 PM PDT 24 136882564 ps
T109 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2795005292 Mar 10 01:13:03 PM PDT 24 Mar 10 01:13:04 PM PDT 24 37242280 ps
T70 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1425447848 Mar 10 01:13:17 PM PDT 24 Mar 10 01:13:22 PM PDT 24 6184960107 ps
T274 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3740463654 Mar 10 01:13:02 PM PDT 24 Mar 10 01:13:08 PM PDT 24 116814390 ps
T275 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3773343040 Mar 10 01:12:50 PM PDT 24 Mar 10 01:12:51 PM PDT 24 84211481 ps
T276 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2584178965 Mar 10 01:12:45 PM PDT 24 Mar 10 01:12:46 PM PDT 24 56522665 ps
T277 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3089289322 Mar 10 01:13:09 PM PDT 24 Mar 10 01:13:12 PM PDT 24 419711404 ps
T278 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1034501553 Mar 10 01:12:50 PM PDT 24 Mar 10 01:12:51 PM PDT 24 304007873 ps
T279 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.341781499 Mar 10 01:12:52 PM PDT 24 Mar 10 01:12:53 PM PDT 24 198897922 ps
T280 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.571762549 Mar 10 01:12:59 PM PDT 24 Mar 10 01:13:15 PM PDT 24 7403486444 ps
T281 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3795005472 Mar 10 01:12:53 PM PDT 24 Mar 10 01:12:56 PM PDT 24 336678581 ps
T282 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1303954479 Mar 10 01:13:02 PM PDT 24 Mar 10 01:13:03 PM PDT 24 44001927 ps
T283 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1609429403 Mar 10 01:12:47 PM PDT 24 Mar 10 01:12:48 PM PDT 24 31035909 ps
T284 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4044338446 Mar 10 01:13:03 PM PDT 24 Mar 10 01:13:05 PM PDT 24 498656049 ps
T285 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.751699049 Mar 10 01:13:02 PM PDT 24 Mar 10 01:13:04 PM PDT 24 192600801 ps
T110 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2628488789 Mar 10 01:12:49 PM PDT 24 Mar 10 01:12:52 PM PDT 24 382768573 ps
T286 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3421435391 Mar 10 01:13:02 PM PDT 24 Mar 10 01:13:03 PM PDT 24 61545325 ps
T111 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3078550640 Mar 10 01:12:51 PM PDT 24 Mar 10 01:13:21 PM PDT 24 3370082784 ps
T287 /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.31586469 Mar 10 01:13:04 PM PDT 24 Mar 10 01:13:19 PM PDT 24 8060429537 ps
T112 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1127217853 Mar 10 01:12:51 PM PDT 24 Mar 10 01:13:59 PM PDT 24 10757773660 ps
T288 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1748540299 Mar 10 01:13:08 PM PDT 24 Mar 10 01:13:11 PM PDT 24 271691313 ps
T127 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2938140122 Mar 10 01:13:01 PM PDT 24 Mar 10 01:13:22 PM PDT 24 4929762208 ps
T289 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1801094281 Mar 10 01:12:37 PM PDT 24 Mar 10 01:12:42 PM PDT 24 1129446311 ps
T290 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1724174122 Mar 10 01:13:02 PM PDT 24 Mar 10 01:13:04 PM PDT 24 204856587 ps
T291 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1191082062 Mar 10 01:12:45 PM PDT 24 Mar 10 01:12:47 PM PDT 24 80627058 ps
T292 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1133222933 Mar 10 01:12:54 PM PDT 24 Mar 10 01:13:01 PM PDT 24 4728107370 ps
T293 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3179357812 Mar 10 01:13:04 PM PDT 24 Mar 10 01:13:06 PM PDT 24 100660159 ps
T294 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.4069227492 Mar 10 01:12:43 PM PDT 24 Mar 10 01:12:45 PM PDT 24 32451203 ps
T295 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3702508804 Mar 10 01:12:42 PM PDT 24 Mar 10 01:12:43 PM PDT 24 30980380 ps
T296 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2498128761 Mar 10 01:13:07 PM PDT 24 Mar 10 01:13:10 PM PDT 24 53977971 ps
T297 /workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.3537349901 Mar 10 01:13:11 PM PDT 24 Mar 10 01:13:29 PM PDT 24 16601088272 ps
T298 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.780239833 Mar 10 01:13:09 PM PDT 24 Mar 10 01:13:19 PM PDT 24 4111112251 ps
T299 /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.3642899198 Mar 10 01:13:15 PM PDT 24 Mar 10 01:13:59 PM PDT 24 13822294877 ps
T300 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.990707591 Mar 10 01:13:06 PM PDT 24 Mar 10 01:13:14 PM PDT 24 243754423 ps
T126 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3888793536 Mar 10 01:12:57 PM PDT 24 Mar 10 01:13:14 PM PDT 24 1554905100 ps
T301 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1275527259 Mar 10 01:13:07 PM PDT 24 Mar 10 01:13:08 PM PDT 24 91582566 ps
T302 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2051843641 Mar 10 01:12:56 PM PDT 24 Mar 10 01:12:57 PM PDT 24 53425023 ps
T303 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3469862633 Mar 10 01:12:50 PM PDT 24 Mar 10 01:12:52 PM PDT 24 939409096 ps
T304 /workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.2283964886 Mar 10 01:13:22 PM PDT 24 Mar 10 01:13:34 PM PDT 24 14392607889 ps
T122 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3929466591 Mar 10 01:12:39 PM PDT 24 Mar 10 01:12:44 PM PDT 24 385878165 ps
T305 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3636511462 Mar 10 01:12:52 PM PDT 24 Mar 10 01:13:19 PM PDT 24 1473763398 ps
T306 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.245217256 Mar 10 01:12:54 PM PDT 24 Mar 10 01:12:56 PM PDT 24 25458095 ps
T114 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.122545942 Mar 10 01:12:38 PM PDT 24 Mar 10 01:13:51 PM PDT 24 13265789980 ps
T307 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2000670199 Mar 10 01:12:39 PM PDT 24 Mar 10 01:12:40 PM PDT 24 90818760 ps
T308 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1567284463 Mar 10 01:12:56 PM PDT 24 Mar 10 01:12:58 PM PDT 24 237147063 ps
T309 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.519259414 Mar 10 01:12:50 PM PDT 24 Mar 10 01:13:08 PM PDT 24 2109529163 ps
T310 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2198828155 Mar 10 01:12:59 PM PDT 24 Mar 10 01:13:50 PM PDT 24 27107026351 ps
T311 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2885899118 Mar 10 01:12:54 PM PDT 24 Mar 10 01:13:01 PM PDT 24 2449896145 ps
T312 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.4001405825 Mar 10 01:13:02 PM PDT 24 Mar 10 01:13:03 PM PDT 24 46031664 ps
T132 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1512058477 Mar 10 01:12:51 PM PDT 24 Mar 10 01:12:59 PM PDT 24 681512477 ps
T313 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2502935755 Mar 10 01:13:05 PM PDT 24 Mar 10 01:13:06 PM PDT 24 293517547 ps
T314 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2258843097 Mar 10 01:13:03 PM PDT 24 Mar 10 01:13:05 PM PDT 24 96262430 ps
T315 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2602742888 Mar 10 01:12:49 PM PDT 24 Mar 10 01:12:50 PM PDT 24 171410848 ps
T115 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3272470934 Mar 10 01:12:38 PM PDT 24 Mar 10 01:12:41 PM PDT 24 460404246 ps
T316 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.994168019 Mar 10 01:13:01 PM PDT 24 Mar 10 01:13:03 PM PDT 24 567539647 ps
T317 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3363861831 Mar 10 01:12:59 PM PDT 24 Mar 10 01:13:01 PM PDT 24 451546981 ps
T318 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1492686656 Mar 10 01:12:35 PM PDT 24 Mar 10 01:12:37 PM PDT 24 42382969 ps
T319 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1645282400 Mar 10 01:12:38 PM PDT 24 Mar 10 01:12:42 PM PDT 24 90700694 ps
T320 /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.3538632501 Mar 10 01:13:11 PM PDT 24 Mar 10 01:13:50 PM PDT 24 12186311701 ps
T128 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2997572815 Mar 10 01:13:08 PM PDT 24 Mar 10 01:13:27 PM PDT 24 1800379598 ps
T321 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1721092581 Mar 10 01:13:01 PM PDT 24 Mar 10 01:13:13 PM PDT 24 4866370997 ps
T322 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2018659501 Mar 10 01:13:07 PM PDT 24 Mar 10 01:13:09 PM PDT 24 343486384 ps
T323 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3418953109 Mar 10 01:13:06 PM PDT 24 Mar 10 01:13:08 PM PDT 24 625188409 ps
T324 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.4162825488 Mar 10 01:12:38 PM PDT 24 Mar 10 01:13:02 PM PDT 24 4911002781 ps
T325 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2015116812 Mar 10 01:12:51 PM PDT 24 Mar 10 01:12:52 PM PDT 24 319128657 ps
T326 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3864573116 Mar 10 01:12:45 PM PDT 24 Mar 10 01:13:13 PM PDT 24 2822297215 ps
T134 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1467899835 Mar 10 01:13:06 PM PDT 24 Mar 10 01:13:26 PM PDT 24 3339018813 ps
T327 /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.3476136308 Mar 10 01:13:09 PM PDT 24 Mar 10 01:13:45 PM PDT 24 8573205347 ps
T328 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.4294342669 Mar 10 01:12:47 PM PDT 24 Mar 10 01:12:51 PM PDT 24 222488840 ps
T103 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2370081372 Mar 10 01:12:51 PM PDT 24 Mar 10 01:12:55 PM PDT 24 302303727 ps
T329 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1595309935 Mar 10 01:13:13 PM PDT 24 Mar 10 01:13:15 PM PDT 24 70919102 ps
T330 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1518011977 Mar 10 01:12:57 PM PDT 24 Mar 10 01:13:03 PM PDT 24 4839087454 ps
T133 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2270409409 Mar 10 01:12:53 PM PDT 24 Mar 10 01:13:02 PM PDT 24 299234059 ps
T331 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1132196204 Mar 10 01:12:55 PM PDT 24 Mar 10 01:12:59 PM PDT 24 1071679685 ps
T332 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2889354697 Mar 10 01:13:06 PM PDT 24 Mar 10 01:13:11 PM PDT 24 1601250787 ps
T333 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1278342023 Mar 10 01:13:17 PM PDT 24 Mar 10 01:13:28 PM PDT 24 5239558466 ps
T334 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1282778767 Mar 10 01:12:48 PM PDT 24 Mar 10 01:12:51 PM PDT 24 119425417 ps
T99 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.44643166 Mar 10 01:12:59 PM PDT 24 Mar 10 01:13:02 PM PDT 24 358551929 ps
T335 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3739159462 Mar 10 01:13:09 PM PDT 24 Mar 10 01:13:11 PM PDT 24 463014985 ps
T336 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1624870364 Mar 10 01:12:37 PM PDT 24 Mar 10 01:12:39 PM PDT 24 67432005 ps
T104 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2165764606 Mar 10 01:13:24 PM PDT 24 Mar 10 01:13:31 PM PDT 24 287497321 ps
T105 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.497365826 Mar 10 01:12:54 PM PDT 24 Mar 10 01:12:59 PM PDT 24 432169107 ps
T337 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2185126898 Mar 10 01:12:53 PM PDT 24 Mar 10 01:12:55 PM PDT 24 90121204 ps
T338 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1374903272 Mar 10 01:12:37 PM PDT 24 Mar 10 01:12:38 PM PDT 24 53801337 ps
T339 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4181646339 Mar 10 01:12:54 PM PDT 24 Mar 10 01:12:58 PM PDT 24 246317596 ps
T340 /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.1212847314 Mar 10 01:13:12 PM PDT 24 Mar 10 01:13:27 PM PDT 24 24214515848 ps
T341 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2347767649 Mar 10 01:12:39 PM PDT 24 Mar 10 01:12:40 PM PDT 24 34600372 ps
T342 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.485300154 Mar 10 01:13:05 PM PDT 24 Mar 10 01:13:06 PM PDT 24 770272211 ps
T343 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4232414752 Mar 10 01:12:54 PM PDT 24 Mar 10 01:14:03 PM PDT 24 14718283063 ps
T106 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2195756859 Mar 10 01:12:57 PM PDT 24 Mar 10 01:13:02 PM PDT 24 226099564 ps
T344 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1728299202 Mar 10 01:12:51 PM PDT 24 Mar 10 01:13:02 PM PDT 24 6542187751 ps
T345 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3036185122 Mar 10 01:12:54 PM PDT 24 Mar 10 01:12:56 PM PDT 24 165674646 ps
T346 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1486444946 Mar 10 01:13:04 PM PDT 24 Mar 10 01:13:07 PM PDT 24 108414378 ps
T347 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2123116108 Mar 10 01:13:06 PM PDT 24 Mar 10 01:13:07 PM PDT 24 133570428 ps
T348 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1032312282 Mar 10 01:13:06 PM PDT 24 Mar 10 01:13:16 PM PDT 24 506538222 ps
T349 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2852332293 Mar 10 01:12:53 PM PDT 24 Mar 10 01:13:01 PM PDT 24 1331199000 ps
T350 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2106564017 Mar 10 01:13:10 PM PDT 24 Mar 10 01:13:13 PM PDT 24 302559208 ps
T351 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2913335791 Mar 10 01:12:44 PM PDT 24 Mar 10 01:12:54 PM PDT 24 3041394266 ps
T352 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1549729939 Mar 10 01:13:26 PM PDT 24 Mar 10 01:13:31 PM PDT 24 180762088 ps
T353 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1799253269 Mar 10 01:12:55 PM PDT 24 Mar 10 01:12:57 PM PDT 24 118233253 ps
T116 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2643504723 Mar 10 01:12:58 PM PDT 24 Mar 10 01:13:00 PM PDT 24 35308448 ps
T354 /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.1278026019 Mar 10 01:13:03 PM PDT 24 Mar 10 01:13:13 PM PDT 24 10606982175 ps
T100 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2188667154 Mar 10 01:12:42 PM PDT 24 Mar 10 01:12:47 PM PDT 24 1056395079 ps
T355 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2430935289 Mar 10 01:13:05 PM PDT 24 Mar 10 01:13:06 PM PDT 24 28775311 ps
T356 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.50269039 Mar 10 01:13:06 PM PDT 24 Mar 10 01:13:07 PM PDT 24 130288854 ps
T357 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.4121507836 Mar 10 01:12:54 PM PDT 24 Mar 10 01:12:56 PM PDT 24 47360119 ps
T358 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4125077182 Mar 10 01:13:07 PM PDT 24 Mar 10 01:13:10 PM PDT 24 326963042 ps
T359 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2030175066 Mar 10 01:13:06 PM PDT 24 Mar 10 01:13:17 PM PDT 24 607607346 ps
T360 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2024611405 Mar 10 01:13:04 PM PDT 24 Mar 10 01:13:08 PM PDT 24 4150832311 ps
T361 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3085866896 Mar 10 01:13:06 PM PDT 24 Mar 10 01:13:10 PM PDT 24 62957400 ps
T362 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1715230606 Mar 10 01:13:08 PM PDT 24 Mar 10 01:13:09 PM PDT 24 145862789 ps
T363 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.36494482 Mar 10 01:12:40 PM PDT 24 Mar 10 01:12:45 PM PDT 24 455567653 ps
T364 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2962460665 Mar 10 01:12:36 PM PDT 24 Mar 10 01:12:39 PM PDT 24 102885509 ps
T365 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.307030707 Mar 10 01:12:59 PM PDT 24 Mar 10 01:13:12 PM PDT 24 10620950601 ps
T366 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1111200165 Mar 10 01:12:43 PM PDT 24 Mar 10 01:12:45 PM PDT 24 1128527312 ps
T367 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1875142412 Mar 10 01:13:07 PM PDT 24 Mar 10 01:13:15 PM PDT 24 795007244 ps
T368 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.883414365 Mar 10 01:12:53 PM PDT 24 Mar 10 01:12:58 PM PDT 24 844809827 ps
T369 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.932177345 Mar 10 01:13:05 PM PDT 24 Mar 10 01:13:06 PM PDT 24 126563161 ps
T370 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.82886574 Mar 10 01:12:37 PM PDT 24 Mar 10 01:13:45 PM PDT 24 1221546389 ps
T117 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2733683248 Mar 10 01:12:59 PM PDT 24 Mar 10 01:13:01 PM PDT 24 284709471 ps
T371 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2482107096 Mar 10 01:12:51 PM PDT 24 Mar 10 01:12:54 PM PDT 24 419957080 ps
T372 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.334384305 Mar 10 01:12:42 PM PDT 24 Mar 10 01:12:59 PM PDT 24 4548107910 ps

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3748388862
Short name T3
Test name
Test status
Simulation time 5759066573 ps
CPU time 17.77 seconds
Started Mar 10 01:10:18 PM PDT 24
Finished Mar 10 01:10:37 PM PDT 24
Peak memory 203768 kb
Host smart-f96bf0fa-0e8f-440c-8ac2-f076232b060a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748388862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3748388862
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3862928985
Short name T51
Test name
Test status
Simulation time 315924371 ps
CPU time 5.04 seconds
Started Mar 10 01:12:54 PM PDT 24
Finished Mar 10 01:13:00 PM PDT 24
Peak memory 212140 kb
Host smart-7037ac47-a2ec-4293-9dd2-01f96cbcdaa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862928985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3862928985
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.3536080749
Short name T6
Test name
Test status
Simulation time 4846248492 ps
CPU time 8.02 seconds
Started Mar 10 01:10:36 PM PDT 24
Finished Mar 10 01:10:45 PM PDT 24
Peak memory 203608 kb
Host smart-de354a97-094b-4553-8c74-d7ba40ce80f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536080749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.3536080749
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.1156924079
Short name T55
Test name
Test status
Simulation time 23374802 ps
CPU time 0.64 seconds
Started Mar 10 01:10:06 PM PDT 24
Finished Mar 10 01:10:07 PM PDT 24
Peak memory 203468 kb
Host smart-18d9b854-e3a4-408d-af47-5cad976b1c16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156924079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1156924079
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.640557351
Short name T48
Test name
Test status
Simulation time 1254914674 ps
CPU time 10.88 seconds
Started Mar 10 01:12:56 PM PDT 24
Finished Mar 10 01:13:08 PM PDT 24
Peak memory 211924 kb
Host smart-4ca4e1ab-88bf-4f4d-a477-95d52e35b660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640557351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.640557351
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tap_fsm_rand_reset.726674284
Short name T135
Test name
Test status
Simulation time 5429612779 ps
CPU time 18.42 seconds
Started Mar 10 01:13:02 PM PDT 24
Finished Mar 10 01:13:21 PM PDT 24
Peak memory 212148 kb
Host smart-da4320ce-a7c7-4026-80a2-5f55dcc1bfeb
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726674284 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rv_dm_tap_fsm_rand_reset.726674284
Directory /workspace/16.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.252058627
Short name T5
Test name
Test status
Simulation time 2136436884 ps
CPU time 5.66 seconds
Started Mar 10 01:10:27 PM PDT 24
Finished Mar 10 01:10:33 PM PDT 24
Peak memory 203540 kb
Host smart-0298de9f-5eac-466a-962a-557fabc4ec92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252058627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.252058627
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.4198502785
Short name T73
Test name
Test status
Simulation time 8358933236 ps
CPU time 41.22 seconds
Started Mar 10 01:09:58 PM PDT 24
Finished Mar 10 01:10:40 PM PDT 24
Peak memory 203776 kb
Host smart-aab38094-25e9-41f1-b4a4-94e6c8edf289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198502785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.4198502785
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.1959873545
Short name T20
Test name
Test status
Simulation time 5766052676 ps
CPU time 5.92 seconds
Started Mar 10 01:10:04 PM PDT 24
Finished Mar 10 01:10:10 PM PDT 24
Peak memory 203604 kb
Host smart-76db99c3-ff2a-47ee-b33d-31e5e3e155bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959873545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.1959873545
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.3532551852
Short name T7
Test name
Test status
Simulation time 96689679 ps
CPU time 0.76 seconds
Started Mar 10 01:10:04 PM PDT 24
Finished Mar 10 01:10:05 PM PDT 24
Peak memory 203328 kb
Host smart-10b79404-3da4-4e1e-bd44-7a3121287fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532551852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.3532551852
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.537973246
Short name T125
Test name
Test status
Simulation time 3164298350 ps
CPU time 19.56 seconds
Started Mar 10 01:13:06 PM PDT 24
Finished Mar 10 01:13:26 PM PDT 24
Peak memory 216040 kb
Host smart-7eec9d52-1548-42ee-84c0-2b19d8f7391d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537973246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.537973246
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2823791243
Short name T56
Test name
Test status
Simulation time 23115228 ps
CPU time 0.71 seconds
Started Mar 10 01:10:33 PM PDT 24
Finished Mar 10 01:10:34 PM PDT 24
Peak memory 203360 kb
Host smart-f3097229-eeb4-4ee3-be48-30a2f1e5a6a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823791243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2823791243
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.3327203435
Short name T4
Test name
Test status
Simulation time 41057727 ps
CPU time 0.77 seconds
Started Mar 10 01:10:04 PM PDT 24
Finished Mar 10 01:10:05 PM PDT 24
Peak memory 203360 kb
Host smart-79c882f2-0ba0-449c-92e1-38b047833d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327203435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3327203435
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.1905145250
Short name T40
Test name
Test status
Simulation time 1358906348 ps
CPU time 4.34 seconds
Started Mar 10 01:09:56 PM PDT 24
Finished Mar 10 01:10:01 PM PDT 24
Peak memory 203348 kb
Host smart-68eea85b-7d2a-4d05-8602-347bd5bb875d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905145250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1905145250
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2965355016
Short name T91
Test name
Test status
Simulation time 15082277254 ps
CPU time 73.69 seconds
Started Mar 10 01:12:47 PM PDT 24
Finished Mar 10 01:14:01 PM PDT 24
Peak memory 203872 kb
Host smart-d3f40aa9-6aec-4ff0-92aa-35b922f4ceda
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965355016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2965355016
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3121605876
Short name T74
Test name
Test status
Simulation time 120712883 ps
CPU time 1.21 seconds
Started Mar 10 01:10:04 PM PDT 24
Finished Mar 10 01:10:06 PM PDT 24
Peak memory 219812 kb
Host smart-335bdcd3-28ea-4fc3-b89e-101674378284
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121605876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3121605876
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2938140122
Short name T127
Test name
Test status
Simulation time 4929762208 ps
CPU time 19.91 seconds
Started Mar 10 01:13:01 PM PDT 24
Finished Mar 10 01:13:22 PM PDT 24
Peak memory 216008 kb
Host smart-c018146c-d911-485a-a6b3-58fec59a99b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938140122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
938140122
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.197531864
Short name T30
Test name
Test status
Simulation time 44967134 ps
CPU time 0.73 seconds
Started Mar 10 01:09:58 PM PDT 24
Finished Mar 10 01:09:59 PM PDT 24
Peak memory 203368 kb
Host smart-501bef28-66a8-4f9c-bdcc-a076613a934f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197531864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.197531864
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2997572815
Short name T128
Test name
Test status
Simulation time 1800379598 ps
CPU time 18.59 seconds
Started Mar 10 01:13:08 PM PDT 24
Finished Mar 10 01:13:27 PM PDT 24
Peak memory 213996 kb
Host smart-681d573a-bcb0-4991-aae3-2503292e6409
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997572815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2
997572815
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.2438311038
Short name T19
Test name
Test status
Simulation time 972924173 ps
CPU time 3.85 seconds
Started Mar 10 01:10:27 PM PDT 24
Finished Mar 10 01:10:31 PM PDT 24
Peak memory 203480 kb
Host smart-7848d88a-1065-43a5-bdf9-3c88f1a48467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438311038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2438311038
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2512232523
Short name T65
Test name
Test status
Simulation time 510592912 ps
CPU time 6.42 seconds
Started Mar 10 01:13:05 PM PDT 24
Finished Mar 10 01:13:12 PM PDT 24
Peak memory 203800 kb
Host smart-9c99ca48-c27f-47ef-a80b-3a4c0d3ae1f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512232523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2512232523
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3764140248
Short name T237
Test name
Test status
Simulation time 97269704 ps
CPU time 0.71 seconds
Started Mar 10 01:12:40 PM PDT 24
Finished Mar 10 01:12:41 PM PDT 24
Peak memory 203468 kb
Host smart-6025b33b-bccc-4c21-9192-1740a19cc5a7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764140248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3764140248
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1425447848
Short name T70
Test name
Test status
Simulation time 6184960107 ps
CPU time 4.65 seconds
Started Mar 10 01:13:17 PM PDT 24
Finished Mar 10 01:13:22 PM PDT 24
Peak memory 219548 kb
Host smart-6d58b2be-2256-45aa-bbf2-9daa6c19b957
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425447848 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1425447848
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.751699049
Short name T285
Test name
Test status
Simulation time 192600801 ps
CPU time 1.57 seconds
Started Mar 10 01:13:02 PM PDT 24
Finished Mar 10 01:13:04 PM PDT 24
Peak memory 212088 kb
Host smart-f6ac933b-ba88-4721-b961-3c14620d0700
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751699049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.751699049
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2519966003
Short name T85
Test name
Test status
Simulation time 4236418613 ps
CPU time 20.28 seconds
Started Mar 10 01:13:03 PM PDT 24
Finished Mar 10 01:13:24 PM PDT 24
Peak memory 216092 kb
Host smart-092d541d-2d24-4f88-bb92-a5fd372fd80e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519966003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2
519966003
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3896258434
Short name T98
Test name
Test status
Simulation time 1124210098 ps
CPU time 4.52 seconds
Started Mar 10 01:12:39 PM PDT 24
Finished Mar 10 01:12:44 PM PDT 24
Peak memory 203664 kb
Host smart-3a268044-c420-47d8-91ab-f10b43d366f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896258434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.3896258434
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3867108829
Short name T22
Test name
Test status
Simulation time 161437224 ps
CPU time 0.87 seconds
Started Mar 10 01:09:58 PM PDT 24
Finished Mar 10 01:09:59 PM PDT 24
Peak memory 202996 kb
Host smart-ec742785-8bb1-4f03-8ed9-8fc1f336a6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867108829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3867108829
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.907706626
Short name T113
Test name
Test status
Simulation time 19395014762 ps
CPU time 67.37 seconds
Started Mar 10 01:12:37 PM PDT 24
Finished Mar 10 01:13:46 PM PDT 24
Peak memory 203728 kb
Host smart-0c48cd5f-a44d-40b6-b0ea-d0af15f489e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907706626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.907706626
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.198836526
Short name T49
Test name
Test status
Simulation time 788999016 ps
CPU time 16.75 seconds
Started Mar 10 01:12:42 PM PDT 24
Finished Mar 10 01:12:59 PM PDT 24
Peak memory 212092 kb
Host smart-7fba1146-d1a0-4049-8214-44bdf5065509
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198836526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.198836526
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.923482769
Short name T16
Test name
Test status
Simulation time 267830375 ps
CPU time 0.9 seconds
Started Mar 10 01:10:05 PM PDT 24
Finished Mar 10 01:10:06 PM PDT 24
Peak memory 203320 kb
Host smart-18e9fe40-bf94-48a9-84ce-0a509295f35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923482769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.923482769
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.3343687418
Short name T150
Test name
Test status
Simulation time 25797037 ps
CPU time 0.64 seconds
Started Mar 10 01:10:20 PM PDT 24
Finished Mar 10 01:10:21 PM PDT 24
Peak memory 203416 kb
Host smart-8ca77241-b1a0-4663-8bb3-23300622be82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343687418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3343687418
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.82886574
Short name T370
Test name
Test status
Simulation time 1221546389 ps
CPU time 67.88 seconds
Started Mar 10 01:12:37 PM PDT 24
Finished Mar 10 01:13:45 PM PDT 24
Peak memory 211844 kb
Host smart-0bf0b4d8-a9db-4f47-bf02-b600c958e12e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82886574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UV
M_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.rv_dm_csr_aliasing.82886574
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3272470934
Short name T115
Test name
Test status
Simulation time 460404246 ps
CPU time 2.4 seconds
Started Mar 10 01:12:38 PM PDT 24
Finished Mar 10 01:12:41 PM PDT 24
Peak memory 203692 kb
Host smart-52297384-abeb-4541-9d51-376233d5d705
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272470934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3272470934
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1111200165
Short name T366
Test name
Test status
Simulation time 1128527312 ps
CPU time 2.55 seconds
Started Mar 10 01:12:43 PM PDT 24
Finished Mar 10 01:12:45 PM PDT 24
Peak memory 213244 kb
Host smart-6b799143-6175-42ec-9156-f310f0c20bd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111200165 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1111200165
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2962460665
Short name T364
Test name
Test status
Simulation time 102885509 ps
CPU time 2.41 seconds
Started Mar 10 01:12:36 PM PDT 24
Finished Mar 10 01:12:39 PM PDT 24
Peak memory 211964 kb
Host smart-1295729d-bed2-41f0-bb5b-f7558e62193c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962460665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2962460665
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.4162825488
Short name T324
Test name
Test status
Simulation time 4911002781 ps
CPU time 23.54 seconds
Started Mar 10 01:12:38 PM PDT 24
Finished Mar 10 01:13:02 PM PDT 24
Peak memory 203764 kb
Host smart-30072e5d-cc1c-4d5d-b747-998a9fa6df9a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162825488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.4162825488
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1243986293
Short name T250
Test name
Test status
Simulation time 376552584 ps
CPU time 0.94 seconds
Started Mar 10 01:12:42 PM PDT 24
Finished Mar 10 01:12:44 PM PDT 24
Peak memory 203632 kb
Host smart-32f67f42-0083-411d-8fe0-b35831f1c336
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243986293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
243986293
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1879893865
Short name T80
Test name
Test status
Simulation time 2637446185 ps
CPU time 4.8 seconds
Started Mar 10 01:12:35 PM PDT 24
Finished Mar 10 01:12:41 PM PDT 24
Peak memory 203688 kb
Host smart-be515a38-6567-4308-b702-7e9978fe2957
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879893865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1879893865
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1374903272
Short name T338
Test name
Test status
Simulation time 53801337 ps
CPU time 0.73 seconds
Started Mar 10 01:12:37 PM PDT 24
Finished Mar 10 01:12:38 PM PDT 24
Peak memory 203456 kb
Host smart-3fed0e59-bc9f-4c22-a753-14459bc5a085
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374903272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1374903272
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3516491773
Short name T241
Test name
Test status
Simulation time 83451354 ps
CPU time 0.68 seconds
Started Mar 10 01:12:37 PM PDT 24
Finished Mar 10 01:12:38 PM PDT 24
Peak memory 203376 kb
Host smart-4784e757-db08-4a25-a481-f732f25bc16c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516491773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3
516491773
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3727081411
Short name T236
Test name
Test status
Simulation time 17943338 ps
CPU time 0.66 seconds
Started Mar 10 01:12:34 PM PDT 24
Finished Mar 10 01:12:35 PM PDT 24
Peak memory 203588 kb
Host smart-0a683dce-5ae4-443d-bd0a-cc3457ed5eaf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727081411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.3727081411
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1492686656
Short name T318
Test name
Test status
Simulation time 42382969 ps
CPU time 0.65 seconds
Started Mar 10 01:12:35 PM PDT 24
Finished Mar 10 01:12:37 PM PDT 24
Peak memory 203472 kb
Host smart-9db548a1-a95a-453f-8f50-cc3b4ea0adf6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492686656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1492686656
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3929466591
Short name T122
Test name
Test status
Simulation time 385878165 ps
CPU time 3.95 seconds
Started Mar 10 01:12:39 PM PDT 24
Finished Mar 10 01:12:44 PM PDT 24
Peak memory 203828 kb
Host smart-3c099e15-1eb2-4380-9173-ab26dadd6b7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929466591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.3929466591
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1645282400
Short name T319
Test name
Test status
Simulation time 90700694 ps
CPU time 3.26 seconds
Started Mar 10 01:12:38 PM PDT 24
Finished Mar 10 01:12:42 PM PDT 24
Peak memory 203964 kb
Host smart-f7951505-2634-4e82-84de-eb4bf36643c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645282400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1645282400
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1275023732
Short name T68
Test name
Test status
Simulation time 1768942376 ps
CPU time 10.39 seconds
Started Mar 10 01:12:37 PM PDT 24
Finished Mar 10 01:12:48 PM PDT 24
Peak memory 212312 kb
Host smart-9258fe11-70cd-4766-8c12-f660195e7060
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275023732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1275023732
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.122545942
Short name T114
Test name
Test status
Simulation time 13265789980 ps
CPU time 72.48 seconds
Started Mar 10 01:12:38 PM PDT 24
Finished Mar 10 01:13:51 PM PDT 24
Peak memory 204072 kb
Host smart-7383a9c0-c854-4695-b67b-f0048cfe4e1c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122545942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.rv_dm_csr_aliasing.122545942
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3864573116
Short name T326
Test name
Test status
Simulation time 2822297215 ps
CPU time 27.76 seconds
Started Mar 10 01:12:45 PM PDT 24
Finished Mar 10 01:13:13 PM PDT 24
Peak memory 203812 kb
Host smart-03db9db1-30eb-4f56-92fa-0fa12d6ebf61
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864573116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3864573116
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3483867499
Short name T108
Test name
Test status
Simulation time 123327692 ps
CPU time 2.42 seconds
Started Mar 10 01:12:41 PM PDT 24
Finished Mar 10 01:12:43 PM PDT 24
Peak memory 203704 kb
Host smart-d8f82b67-7c79-4758-b6f5-248c7d258c93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483867499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3483867499
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1191082062
Short name T291
Test name
Test status
Simulation time 80627058 ps
CPU time 2.09 seconds
Started Mar 10 01:12:45 PM PDT 24
Finished Mar 10 01:12:47 PM PDT 24
Peak memory 212092 kb
Host smart-591398bb-1fa8-4285-bffd-136d434e6196
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191082062 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1191082062
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2619485245
Short name T107
Test name
Test status
Simulation time 99450496 ps
CPU time 2.29 seconds
Started Mar 10 01:12:50 PM PDT 24
Finished Mar 10 01:12:53 PM PDT 24
Peak memory 203776 kb
Host smart-5b38aca1-ac22-447a-a07b-719cd85b8cc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619485245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2619485245
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.334384305
Short name T372
Test name
Test status
Simulation time 4548107910 ps
CPU time 16.4 seconds
Started Mar 10 01:12:42 PM PDT 24
Finished Mar 10 01:12:59 PM PDT 24
Peak memory 203652 kb
Host smart-ece93678-15cb-45ab-b570-037ebf22d7b0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334384305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_aliasing.334384305
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1197596682
Short name T238
Test name
Test status
Simulation time 14948510229 ps
CPU time 30.94 seconds
Started Mar 10 01:12:40 PM PDT 24
Finished Mar 10 01:13:12 PM PDT 24
Peak memory 203760 kb
Host smart-e3b3918c-1fbf-4e7c-bc63-b22f112c5051
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197596682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.1197596682
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2188667154
Short name T100
Test name
Test status
Simulation time 1056395079 ps
CPU time 4.03 seconds
Started Mar 10 01:12:42 PM PDT 24
Finished Mar 10 01:12:47 PM PDT 24
Peak memory 203708 kb
Host smart-3d2a9ffb-f7fe-4db2-a92a-f7553fdf0baf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188667154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.2188667154
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1518242484
Short name T249
Test name
Test status
Simulation time 396985525 ps
CPU time 2.09 seconds
Started Mar 10 01:12:43 PM PDT 24
Finished Mar 10 01:12:46 PM PDT 24
Peak memory 203616 kb
Host smart-868d2688-b794-4787-8b20-f845d781d995
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518242484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
518242484
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2726737320
Short name T81
Test name
Test status
Simulation time 120870764 ps
CPU time 0.91 seconds
Started Mar 10 01:12:37 PM PDT 24
Finished Mar 10 01:12:39 PM PDT 24
Peak memory 203536 kb
Host smart-a5b278e2-e4eb-4b4f-8619-e6cb0a080ccb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726737320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2726737320
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1801094281
Short name T289
Test name
Test status
Simulation time 1129446311 ps
CPU time 5.01 seconds
Started Mar 10 01:12:37 PM PDT 24
Finished Mar 10 01:12:42 PM PDT 24
Peak memory 203576 kb
Host smart-78d7d2e0-5723-4414-934e-f2f57ca4d5fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801094281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.1801094281
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2347767649
Short name T341
Test name
Test status
Simulation time 34600372 ps
CPU time 0.73 seconds
Started Mar 10 01:12:39 PM PDT 24
Finished Mar 10 01:12:40 PM PDT 24
Peak memory 203684 kb
Host smart-6db7b932-8f39-411d-858c-959d2a9fedfd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347767649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2347767649
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1624870364
Short name T336
Test name
Test status
Simulation time 67432005 ps
CPU time 0.66 seconds
Started Mar 10 01:12:37 PM PDT 24
Finished Mar 10 01:12:39 PM PDT 24
Peak memory 203720 kb
Host smart-f0656fb0-93e3-4c57-b329-22b08d9abfa9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624870364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1
624870364
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2000670199
Short name T307
Test name
Test status
Simulation time 90818760 ps
CPU time 0.76 seconds
Started Mar 10 01:12:39 PM PDT 24
Finished Mar 10 01:12:40 PM PDT 24
Peak memory 203532 kb
Host smart-076e2141-f64f-4509-ab85-fe9a9d653a9a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000670199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2000670199
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3702508804
Short name T295
Test name
Test status
Simulation time 30980380 ps
CPU time 0.64 seconds
Started Mar 10 01:12:42 PM PDT 24
Finished Mar 10 01:12:43 PM PDT 24
Peak memory 203528 kb
Host smart-a8384aef-0048-4d33-8b21-44ada9cb90f3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702508804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3702508804
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2610309131
Short name T118
Test name
Test status
Simulation time 778620669 ps
CPU time 3.7 seconds
Started Mar 10 01:12:46 PM PDT 24
Finished Mar 10 01:12:50 PM PDT 24
Peak memory 203880 kb
Host smart-31f03a69-e23e-4daa-aeb5-b6e3bb4bfa2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610309131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.2610309131
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.36494482
Short name T363
Test name
Test status
Simulation time 455567653 ps
CPU time 4.98 seconds
Started Mar 10 01:12:40 PM PDT 24
Finished Mar 10 01:12:45 PM PDT 24
Peak memory 212144 kb
Host smart-de2f7060-f6ce-4edc-a880-5df7e2c302ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36494482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.36494482
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1724174122
Short name T290
Test name
Test status
Simulation time 204856587 ps
CPU time 1.69 seconds
Started Mar 10 01:13:02 PM PDT 24
Finished Mar 10 01:13:04 PM PDT 24
Peak memory 211960 kb
Host smart-26c479c3-8daa-40e3-9852-f0117f1348db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724174122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1724174122
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.485300154
Short name T342
Test name
Test status
Simulation time 770272211 ps
CPU time 0.91 seconds
Started Mar 10 01:13:05 PM PDT 24
Finished Mar 10 01:13:06 PM PDT 24
Peak memory 203700 kb
Host smart-58618c9b-509b-41db-9409-b962efc0058f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485300154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.485300154
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1275527259
Short name T301
Test name
Test status
Simulation time 91582566 ps
CPU time 0.77 seconds
Started Mar 10 01:13:07 PM PDT 24
Finished Mar 10 01:13:08 PM PDT 24
Peak memory 203476 kb
Host smart-6c6bcc1e-5440-4af4-9a10-cdbd68f76530
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275527259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
1275527259
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3538194186
Short name T120
Test name
Test status
Simulation time 1212131872 ps
CPU time 7.98 seconds
Started Mar 10 01:13:01 PM PDT 24
Finished Mar 10 01:13:10 PM PDT 24
Peak memory 203832 kb
Host smart-93cb3eaf-671c-4011-a2e7-4eede7a3ea2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538194186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3538194186
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3740463654
Short name T274
Test name
Test status
Simulation time 116814390 ps
CPU time 5.73 seconds
Started Mar 10 01:13:02 PM PDT 24
Finished Mar 10 01:13:08 PM PDT 24
Peak memory 212196 kb
Host smart-ad781fec-28ff-47d3-b2de-a12c087ec848
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740463654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3740463654
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2498128761
Short name T296
Test name
Test status
Simulation time 53977971 ps
CPU time 2.87 seconds
Started Mar 10 01:13:07 PM PDT 24
Finished Mar 10 01:13:10 PM PDT 24
Peak memory 219352 kb
Host smart-34e5aa13-6694-49f8-b4b5-d935251cfbad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498128761 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.2498128761
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2430935289
Short name T355
Test name
Test status
Simulation time 28775311 ps
CPU time 1.39 seconds
Started Mar 10 01:13:05 PM PDT 24
Finished Mar 10 01:13:06 PM PDT 24
Peak memory 203684 kb
Host smart-917f0243-fabe-4f16-8c95-a6177a3ff969
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430935289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2430935289
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1715230606
Short name T362
Test name
Test status
Simulation time 145862789 ps
CPU time 1.12 seconds
Started Mar 10 01:13:08 PM PDT 24
Finished Mar 10 01:13:09 PM PDT 24
Peak memory 203692 kb
Host smart-868f9e9d-9eca-4455-98b8-c5879d0e13d5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715230606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
1715230606
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1303954479
Short name T282
Test name
Test status
Simulation time 44001927 ps
CPU time 0.69 seconds
Started Mar 10 01:13:02 PM PDT 24
Finished Mar 10 01:13:03 PM PDT 24
Peak memory 203520 kb
Host smart-b2edc2c6-c669-4a38-b1de-16f60074bb79
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303954479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1303954479
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.827011965
Short name T93
Test name
Test status
Simulation time 1188001394 ps
CPU time 4.65 seconds
Started Mar 10 01:13:02 PM PDT 24
Finished Mar 10 01:13:07 PM PDT 24
Peak memory 203848 kb
Host smart-1423a936-99f7-4e87-878a-6bd1615c9c11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827011965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.827011965
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.2283964886
Short name T304
Test name
Test status
Simulation time 14392607889 ps
CPU time 12.15 seconds
Started Mar 10 01:13:22 PM PDT 24
Finished Mar 10 01:13:34 PM PDT 24
Peak memory 212160 kb
Host smart-a5714745-2c84-49f0-8f6f-bf035e46df74
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283964886 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rv_dm_tap_fsm_rand_reset.2283964886
Directory /workspace/11.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2018659501
Short name T322
Test name
Test status
Simulation time 343486384 ps
CPU time 2.11 seconds
Started Mar 10 01:13:07 PM PDT 24
Finished Mar 10 01:13:09 PM PDT 24
Peak memory 203932 kb
Host smart-fb78664a-143c-4075-9969-b12a88606152
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018659501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2018659501
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.521679566
Short name T129
Test name
Test status
Simulation time 3664981930 ps
CPU time 18.02 seconds
Started Mar 10 01:13:04 PM PDT 24
Finished Mar 10 01:13:22 PM PDT 24
Peak memory 212684 kb
Host smart-191daf3a-f48b-4abf-911f-37a3e0a140b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521679566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.521679566
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3340062911
Short name T69
Test name
Test status
Simulation time 1143155191 ps
CPU time 5.66 seconds
Started Mar 10 01:13:04 PM PDT 24
Finished Mar 10 01:13:10 PM PDT 24
Peak memory 215512 kb
Host smart-05265a0f-5e73-411b-96e0-32db98ee80bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340062911 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3340062911
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3179357812
Short name T293
Test name
Test status
Simulation time 100660159 ps
CPU time 1.53 seconds
Started Mar 10 01:13:04 PM PDT 24
Finished Mar 10 01:13:06 PM PDT 24
Peak memory 203752 kb
Host smart-d4f87dbb-eae6-4ed0-a4dc-afacea992314
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179357812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3179357812
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.994168019
Short name T316
Test name
Test status
Simulation time 567539647 ps
CPU time 1.24 seconds
Started Mar 10 01:13:01 PM PDT 24
Finished Mar 10 01:13:03 PM PDT 24
Peak memory 203604 kb
Host smart-4041dd26-e1d9-4cad-a015-7aab53eecdf4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994168019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.994168019
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.4001405825
Short name T312
Test name
Test status
Simulation time 46031664 ps
CPU time 0.75 seconds
Started Mar 10 01:13:02 PM PDT 24
Finished Mar 10 01:13:03 PM PDT 24
Peak memory 203516 kb
Host smart-83846244-0971-4af2-b043-3a537ecaa764
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001405825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
4001405825
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1584577409
Short name T67
Test name
Test status
Simulation time 306155235 ps
CPU time 4 seconds
Started Mar 10 01:13:12 PM PDT 24
Finished Mar 10 01:13:17 PM PDT 24
Peak memory 203760 kb
Host smart-6a2edc81-724b-43b4-8522-527e1ca8ff22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584577409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1584577409
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.31586469
Short name T287
Test name
Test status
Simulation time 8060429537 ps
CPU time 14.71 seconds
Started Mar 10 01:13:04 PM PDT 24
Finished Mar 10 01:13:19 PM PDT 24
Peak memory 219200 kb
Host smart-dc6863e5-65af-4d1f-964a-d52dd4b7dc96
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31586469 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_tap_fsm_rand_reset.31586469
Directory /workspace/12.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4125077182
Short name T358
Test name
Test status
Simulation time 326963042 ps
CPU time 2.71 seconds
Started Mar 10 01:13:07 PM PDT 24
Finished Mar 10 01:13:10 PM PDT 24
Peak memory 212068 kb
Host smart-edeb33d9-75f1-4b67-9262-32075eb2440e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125077182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.4125077182
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1721092581
Short name T321
Test name
Test status
Simulation time 4866370997 ps
CPU time 11.23 seconds
Started Mar 10 01:13:01 PM PDT 24
Finished Mar 10 01:13:13 PM PDT 24
Peak memory 215808 kb
Host smart-dee2013a-2507-410a-b2cf-b05c24b40d56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721092581 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1721092581
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1486444946
Short name T346
Test name
Test status
Simulation time 108414378 ps
CPU time 2.36 seconds
Started Mar 10 01:13:04 PM PDT 24
Finished Mar 10 01:13:07 PM PDT 24
Peak memory 203768 kb
Host smart-ffd42351-1266-4f48-bbb9-649190e34936
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486444946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1486444946
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2502935755
Short name T313
Test name
Test status
Simulation time 293517547 ps
CPU time 1.22 seconds
Started Mar 10 01:13:05 PM PDT 24
Finished Mar 10 01:13:06 PM PDT 24
Peak memory 203620 kb
Host smart-d7a014a3-99f5-4d9a-9d86-4ef69ee9ccab
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502935755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2502935755
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1703517735
Short name T248
Test name
Test status
Simulation time 43130543 ps
CPU time 0.67 seconds
Started Mar 10 01:13:10 PM PDT 24
Finished Mar 10 01:13:10 PM PDT 24
Peak memory 203460 kb
Host smart-40d73d76-3075-4ac3-ac38-59b37e87d7f9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703517735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1703517735
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1748540299
Short name T288
Test name
Test status
Simulation time 271691313 ps
CPU time 3.58 seconds
Started Mar 10 01:13:08 PM PDT 24
Finished Mar 10 01:13:11 PM PDT 24
Peak memory 203792 kb
Host smart-789fb466-49e1-4203-92dc-804525842cf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748540299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1748540299
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3021562070
Short name T95
Test name
Test status
Simulation time 195072484 ps
CPU time 2.82 seconds
Started Mar 10 01:13:06 PM PDT 24
Finished Mar 10 01:13:09 PM PDT 24
Peak memory 203868 kb
Host smart-da004ec0-9b69-4f08-a13b-f74c0c625e9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021562070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3021562070
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1032312282
Short name T348
Test name
Test status
Simulation time 506538222 ps
CPU time 10.05 seconds
Started Mar 10 01:13:06 PM PDT 24
Finished Mar 10 01:13:16 PM PDT 24
Peak memory 212192 kb
Host smart-50dc08a1-1e88-48e2-ad5d-8eff28d3b895
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032312282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1
032312282
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1448234330
Short name T256
Test name
Test status
Simulation time 575884503 ps
CPU time 3.76 seconds
Started Mar 10 01:13:05 PM PDT 24
Finished Mar 10 01:13:09 PM PDT 24
Peak memory 215600 kb
Host smart-4e24680e-9d92-47ec-b303-8703d0dde8e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448234330 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1448234330
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2258843097
Short name T314
Test name
Test status
Simulation time 96262430 ps
CPU time 2.21 seconds
Started Mar 10 01:13:03 PM PDT 24
Finished Mar 10 01:13:05 PM PDT 24
Peak memory 203604 kb
Host smart-9f7eac7f-76ba-45ae-aa42-9c5bff752412
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258843097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2258843097
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.4184007939
Short name T255
Test name
Test status
Simulation time 199111330 ps
CPU time 1.06 seconds
Started Mar 10 01:13:08 PM PDT 24
Finished Mar 10 01:13:09 PM PDT 24
Peak memory 203660 kb
Host smart-e55e4134-1b14-45e0-83c0-a50e30c2315b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184007939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
4184007939
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3421435391
Short name T286
Test name
Test status
Simulation time 61545325 ps
CPU time 0.71 seconds
Started Mar 10 01:13:02 PM PDT 24
Finished Mar 10 01:13:03 PM PDT 24
Peak memory 203544 kb
Host smart-ae761c32-dd34-47dd-8b70-6cdd20cb4a3c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421435391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
3421435391
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.1278026019
Short name T354
Test name
Test status
Simulation time 10606982175 ps
CPU time 10.33 seconds
Started Mar 10 01:13:03 PM PDT 24
Finished Mar 10 01:13:13 PM PDT 24
Peak memory 219660 kb
Host smart-98ce95b0-3130-4e05-beeb-0b1910700a62
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278026019 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rv_dm_tap_fsm_rand_reset.1278026019
Directory /workspace/14.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2024611405
Short name T360
Test name
Test status
Simulation time 4150832311 ps
CPU time 3.65 seconds
Started Mar 10 01:13:04 PM PDT 24
Finished Mar 10 01:13:08 PM PDT 24
Peak memory 219684 kb
Host smart-ba270a99-91f4-47cf-a410-8e9b2dd80eda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024611405 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2024611405
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3739159462
Short name T335
Test name
Test status
Simulation time 463014985 ps
CPU time 1.51 seconds
Started Mar 10 01:13:09 PM PDT 24
Finished Mar 10 01:13:11 PM PDT 24
Peak memory 203736 kb
Host smart-8501537a-5b3d-4464-8f34-f7aff0f8ed9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739159462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3739159462
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2889354697
Short name T332
Test name
Test status
Simulation time 1601250787 ps
CPU time 5.46 seconds
Started Mar 10 01:13:06 PM PDT 24
Finished Mar 10 01:13:11 PM PDT 24
Peak memory 203568 kb
Host smart-d57c89b4-a492-4a81-b10c-8328b032fc6a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889354697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
2889354697
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.932177345
Short name T369
Test name
Test status
Simulation time 126563161 ps
CPU time 0.71 seconds
Started Mar 10 01:13:05 PM PDT 24
Finished Mar 10 01:13:06 PM PDT 24
Peak memory 203452 kb
Host smart-37882d88-f640-45d4-9bbd-15c4fc7a7166
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932177345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.932177345
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1875142412
Short name T367
Test name
Test status
Simulation time 795007244 ps
CPU time 7.19 seconds
Started Mar 10 01:13:07 PM PDT 24
Finished Mar 10 01:13:15 PM PDT 24
Peak memory 203868 kb
Host smart-a17e2b63-38dd-4a43-9329-d980a2bc74ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875142412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1875142412
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2030175066
Short name T359
Test name
Test status
Simulation time 607607346 ps
CPU time 4.48 seconds
Started Mar 10 01:13:06 PM PDT 24
Finished Mar 10 01:13:17 PM PDT 24
Peak memory 203804 kb
Host smart-6a5f840e-9893-4aa0-8018-b0ff4962e99d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030175066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2030175066
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.990707591
Short name T300
Test name
Test status
Simulation time 243754423 ps
CPU time 8.19 seconds
Started Mar 10 01:13:06 PM PDT 24
Finished Mar 10 01:13:14 PM PDT 24
Peak memory 211840 kb
Host smart-c0c54670-8b80-4daf-8b34-a87abf3fa208
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990707591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.990707591
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.780239833
Short name T298
Test name
Test status
Simulation time 4111112251 ps
CPU time 9.36 seconds
Started Mar 10 01:13:09 PM PDT 24
Finished Mar 10 01:13:19 PM PDT 24
Peak memory 220328 kb
Host smart-75f738b7-1f23-4d75-bf0c-9d928372d45f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780239833 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.780239833
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2795005292
Short name T109
Test name
Test status
Simulation time 37242280 ps
CPU time 1.47 seconds
Started Mar 10 01:13:03 PM PDT 24
Finished Mar 10 01:13:04 PM PDT 24
Peak memory 203796 kb
Host smart-cd5cc9f1-4331-47dd-a7cf-797b146e803c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795005292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2795005292
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3418953109
Short name T323
Test name
Test status
Simulation time 625188409 ps
CPU time 1.29 seconds
Started Mar 10 01:13:06 PM PDT 24
Finished Mar 10 01:13:08 PM PDT 24
Peak memory 203704 kb
Host smart-60af9f5a-32bd-4924-bcbc-d9b5f544a19a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418953109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
3418953109
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1624064772
Short name T269
Test name
Test status
Simulation time 68877819 ps
CPU time 0.85 seconds
Started Mar 10 01:13:09 PM PDT 24
Finished Mar 10 01:13:10 PM PDT 24
Peak memory 203472 kb
Host smart-9c021833-a31e-4e82-98f2-90f364340211
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624064772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
1624064772
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2106564017
Short name T350
Test name
Test status
Simulation time 302559208 ps
CPU time 3.34 seconds
Started Mar 10 01:13:10 PM PDT 24
Finished Mar 10 01:13:13 PM PDT 24
Peak memory 203840 kb
Host smart-1b9ca6f6-3f45-4c11-b235-91b7521d8323
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106564017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.2106564017
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3883463609
Short name T94
Test name
Test status
Simulation time 154794078 ps
CPU time 2.41 seconds
Started Mar 10 01:13:03 PM PDT 24
Finished Mar 10 01:13:05 PM PDT 24
Peak memory 203860 kb
Host smart-cabc967e-2249-4ac5-8899-6b55456f06a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883463609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3883463609
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1467899835
Short name T134
Test name
Test status
Simulation time 3339018813 ps
CPU time 19.25 seconds
Started Mar 10 01:13:06 PM PDT 24
Finished Mar 10 01:13:26 PM PDT 24
Peak memory 216124 kb
Host smart-78360b10-0b14-43df-a581-8138d8961bde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467899835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1
467899835
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3779136096
Short name T273
Test name
Test status
Simulation time 136882564 ps
CPU time 2.19 seconds
Started Mar 10 01:13:19 PM PDT 24
Finished Mar 10 01:13:22 PM PDT 24
Peak memory 212072 kb
Host smart-4f689384-562a-457c-a8a7-8e037bc6ddaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779136096 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.3779136096
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3089289322
Short name T277
Test name
Test status
Simulation time 419711404 ps
CPU time 2.33 seconds
Started Mar 10 01:13:09 PM PDT 24
Finished Mar 10 01:13:12 PM PDT 24
Peak memory 203752 kb
Host smart-d0b9ba6a-d298-4c95-aff5-5bbcd9b50101
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089289322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3089289322
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4044338446
Short name T284
Test name
Test status
Simulation time 498656049 ps
CPU time 2.51 seconds
Started Mar 10 01:13:03 PM PDT 24
Finished Mar 10 01:13:05 PM PDT 24
Peak memory 203600 kb
Host smart-5596e841-756d-4d53-a46f-21069ea736fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044338446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
4044338446
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.107858396
Short name T253
Test name
Test status
Simulation time 92075560 ps
CPU time 0.76 seconds
Started Mar 10 01:13:06 PM PDT 24
Finished Mar 10 01:13:07 PM PDT 24
Peak memory 203476 kb
Host smart-d19e7c70-593a-4d06-8e58-7f627dde4498
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107858396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.107858396
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2165764606
Short name T104
Test name
Test status
Simulation time 287497321 ps
CPU time 6.79 seconds
Started Mar 10 01:13:24 PM PDT 24
Finished Mar 10 01:13:31 PM PDT 24
Peak memory 203812 kb
Host smart-7ac5ddb4-bc59-46c8-ab12-2cba4386b9c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165764606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.2165764606
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.1884982640
Short name T52
Test name
Test status
Simulation time 7196975530 ps
CPU time 12.39 seconds
Started Mar 10 01:13:25 PM PDT 24
Finished Mar 10 01:13:37 PM PDT 24
Peak memory 214940 kb
Host smart-64b74ab2-0159-439b-b847-e2bec78fc4a4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884982640 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rv_dm_tap_fsm_rand_reset.1884982640
Directory /workspace/17.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1549729939
Short name T352
Test name
Test status
Simulation time 180762088 ps
CPU time 4.97 seconds
Started Mar 10 01:13:26 PM PDT 24
Finished Mar 10 01:13:31 PM PDT 24
Peak memory 212112 kb
Host smart-65e6f423-bcc8-48bf-bd85-fc2fa3e90777
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549729939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1549729939
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.823822871
Short name T131
Test name
Test status
Simulation time 1450599183 ps
CPU time 17.18 seconds
Started Mar 10 01:13:03 PM PDT 24
Finished Mar 10 01:13:21 PM PDT 24
Peak memory 212200 kb
Host smart-04300469-9a77-4a5d-9c4b-91ef46f5c07d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823822871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.823822871
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1278342023
Short name T333
Test name
Test status
Simulation time 5239558466 ps
CPU time 11.16 seconds
Started Mar 10 01:13:17 PM PDT 24
Finished Mar 10 01:13:28 PM PDT 24
Peak memory 220336 kb
Host smart-8ce68077-af71-4d8e-9d6a-9b1dbe95c829
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278342023 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1278342023
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.975469839
Short name T92
Test name
Test status
Simulation time 38134548 ps
CPU time 1.43 seconds
Started Mar 10 01:13:07 PM PDT 24
Finished Mar 10 01:13:09 PM PDT 24
Peak memory 212032 kb
Host smart-854aeb4f-d8f3-4d37-836c-f35f8822df96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975469839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.975469839
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.50269039
Short name T356
Test name
Test status
Simulation time 130288854 ps
CPU time 1.22 seconds
Started Mar 10 01:13:06 PM PDT 24
Finished Mar 10 01:13:07 PM PDT 24
Peak memory 203704 kb
Host smart-7930b093-8ffd-4fa7-b7b7-b6ebb6ece6c3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50269039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.50269039
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1315128755
Short name T260
Test name
Test status
Simulation time 68233609 ps
CPU time 0.68 seconds
Started Mar 10 01:13:07 PM PDT 24
Finished Mar 10 01:13:08 PM PDT 24
Peak memory 203444 kb
Host smart-13ba90ba-2b04-4b4b-94cf-8904f71abcb5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315128755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1315128755
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3919856248
Short name T119
Test name
Test status
Simulation time 3520438933 ps
CPU time 7.73 seconds
Started Mar 10 01:13:07 PM PDT 24
Finished Mar 10 01:13:15 PM PDT 24
Peak memory 203816 kb
Host smart-61d8353e-e70e-4303-af8d-b442b4ac24fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919856248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3919856248
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.3476136308
Short name T327
Test name
Test status
Simulation time 8573205347 ps
CPU time 34.84 seconds
Started Mar 10 01:13:09 PM PDT 24
Finished Mar 10 01:13:45 PM PDT 24
Peak memory 219664 kb
Host smart-20b21d06-51cc-4540-a43d-c42911a4fd5e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476136308 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rv_dm_tap_fsm_rand_reset.3476136308
Directory /workspace/18.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2733386646
Short name T72
Test name
Test status
Simulation time 119747549 ps
CPU time 3.42 seconds
Started Mar 10 01:13:07 PM PDT 24
Finished Mar 10 01:13:10 PM PDT 24
Peak memory 212000 kb
Host smart-ada15b0a-dbbd-47e1-aa96-b2efd367525d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733386646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2733386646
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1630615937
Short name T47
Test name
Test status
Simulation time 691080404 ps
CPU time 9.35 seconds
Started Mar 10 01:13:18 PM PDT 24
Finished Mar 10 01:13:28 PM PDT 24
Peak memory 211996 kb
Host smart-6397a914-6d25-46f4-a2c6-118f88c52fa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630615937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1
630615937
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.4252824571
Short name T271
Test name
Test status
Simulation time 5791748175 ps
CPU time 6.15 seconds
Started Mar 10 01:13:09 PM PDT 24
Finished Mar 10 01:13:15 PM PDT 24
Peak memory 220256 kb
Host smart-7c99bb8f-2721-48a8-8954-1c68c441b929
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252824571 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.4252824571
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1595309935
Short name T329
Test name
Test status
Simulation time 70919102 ps
CPU time 1.62 seconds
Started Mar 10 01:13:13 PM PDT 24
Finished Mar 10 01:13:15 PM PDT 24
Peak memory 203752 kb
Host smart-1b8cfb40-8e88-4ab7-9229-2213caf84a39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595309935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1595309935
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2123116108
Short name T347
Test name
Test status
Simulation time 133570428 ps
CPU time 0.98 seconds
Started Mar 10 01:13:06 PM PDT 24
Finished Mar 10 01:13:07 PM PDT 24
Peak memory 203652 kb
Host smart-3fe5e29f-217b-4a3b-ad14-9209ffa555a9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123116108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
2123116108
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1644273639
Short name T246
Test name
Test status
Simulation time 76023142 ps
CPU time 0.67 seconds
Started Mar 10 01:13:13 PM PDT 24
Finished Mar 10 01:13:15 PM PDT 24
Peak memory 203536 kb
Host smart-925d60ed-aa2f-4c1d-8940-23365544517f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644273639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1644273639
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2109264409
Short name T121
Test name
Test status
Simulation time 506950154 ps
CPU time 6.06 seconds
Started Mar 10 01:13:06 PM PDT 24
Finished Mar 10 01:13:12 PM PDT 24
Peak memory 203776 kb
Host smart-22c6d04c-1874-416b-b4d2-6bb8a7ab003c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109264409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.2109264409
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.3537349901
Short name T297
Test name
Test status
Simulation time 16601088272 ps
CPU time 18.01 seconds
Started Mar 10 01:13:11 PM PDT 24
Finished Mar 10 01:13:29 PM PDT 24
Peak memory 212136 kb
Host smart-e0f9d97c-92d6-4f91-a422-9108171b198d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537349901 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rv_dm_tap_fsm_rand_reset.3537349901
Directory /workspace/19.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3085866896
Short name T361
Test name
Test status
Simulation time 62957400 ps
CPU time 3.79 seconds
Started Mar 10 01:13:06 PM PDT 24
Finished Mar 10 01:13:10 PM PDT 24
Peak memory 212140 kb
Host smart-479cdf2d-3bef-4bc4-83f6-d9eef04f8bb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085866896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3085866896
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3356691254
Short name T101
Test name
Test status
Simulation time 2224538736 ps
CPU time 27.94 seconds
Started Mar 10 01:12:47 PM PDT 24
Finished Mar 10 01:13:15 PM PDT 24
Peak memory 203772 kb
Host smart-4871f0f2-8807-4ca1-82c1-c76fd21dadc6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356691254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.3356691254
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3636511462
Short name T305
Test name
Test status
Simulation time 1473763398 ps
CPU time 26.71 seconds
Started Mar 10 01:12:52 PM PDT 24
Finished Mar 10 01:13:19 PM PDT 24
Peak memory 203712 kb
Host smart-95ede25a-27bf-4713-9058-e1b318022261
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636511462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3636511462
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.47347525
Short name T268
Test name
Test status
Simulation time 36611912 ps
CPU time 1.45 seconds
Started Mar 10 01:12:51 PM PDT 24
Finished Mar 10 01:12:53 PM PDT 24
Peak memory 203820 kb
Host smart-257e534f-2b06-41b5-b926-cfe322c18718
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47347525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.47347525
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1004888178
Short name T265
Test name
Test status
Simulation time 1704486243 ps
CPU time 2.89 seconds
Started Mar 10 01:12:52 PM PDT 24
Finished Mar 10 01:12:55 PM PDT 24
Peak memory 212148 kb
Host smart-513613d3-e1e3-4eb3-ad1a-ec95dc55c2c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004888178 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1004888178
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3508006442
Short name T53
Test name
Test status
Simulation time 210578987 ps
CPU time 1.44 seconds
Started Mar 10 01:12:55 PM PDT 24
Finished Mar 10 01:12:58 PM PDT 24
Peak memory 203760 kb
Host smart-68312f09-66fe-4ddd-8efb-41baab0d5558
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508006442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3508006442
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2913335791
Short name T351
Test name
Test status
Simulation time 3041394266 ps
CPU time 9.84 seconds
Started Mar 10 01:12:44 PM PDT 24
Finished Mar 10 01:12:54 PM PDT 24
Peak memory 203660 kb
Host smart-0b2bdbd3-ea8b-4a10-b961-f4038a803a4a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913335791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.2913335791
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1273378667
Short name T96
Test name
Test status
Simulation time 450470966 ps
CPU time 2.1 seconds
Started Mar 10 01:12:55 PM PDT 24
Finished Mar 10 01:12:59 PM PDT 24
Peak memory 203748 kb
Host smart-140d26bd-057b-4697-bbaf-aab929124fc7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273378667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.1273378667
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3119075804
Short name T240
Test name
Test status
Simulation time 1732108051 ps
CPU time 5.86 seconds
Started Mar 10 01:12:52 PM PDT 24
Finished Mar 10 01:12:58 PM PDT 24
Peak memory 203716 kb
Host smart-d73b4171-db24-47ee-9d01-3aeb2b8c7d8c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119075804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3
119075804
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1264794532
Short name T245
Test name
Test status
Simulation time 348248734 ps
CPU time 1.24 seconds
Started Mar 10 01:12:47 PM PDT 24
Finished Mar 10 01:12:48 PM PDT 24
Peak memory 203540 kb
Host smart-a6af27f5-e650-40c3-a170-dd4fb886ddb4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264794532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.1264794532
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.371977149
Short name T239
Test name
Test status
Simulation time 2956442139 ps
CPU time 3.55 seconds
Started Mar 10 01:12:50 PM PDT 24
Finished Mar 10 01:12:53 PM PDT 24
Peak memory 203756 kb
Host smart-ca90cf60-8277-41ac-8eaf-9bb292808bf3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371977149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_bit_bash.371977149
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.4069227492
Short name T294
Test name
Test status
Simulation time 32451203 ps
CPU time 0.71 seconds
Started Mar 10 01:12:43 PM PDT 24
Finished Mar 10 01:12:45 PM PDT 24
Peak memory 203488 kb
Host smart-ba87c6fb-8cb7-47f8-b2eb-1c5f56f9b405
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069227492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.4069227492
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2584178965
Short name T276
Test name
Test status
Simulation time 56522665 ps
CPU time 0.72 seconds
Started Mar 10 01:12:45 PM PDT 24
Finished Mar 10 01:12:46 PM PDT 24
Peak memory 203536 kb
Host smart-83b59f9a-96f7-47ad-a25b-48eed8352ad1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584178965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
584178965
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2479144129
Short name T243
Test name
Test status
Simulation time 48988020 ps
CPU time 0.64 seconds
Started Mar 10 01:12:47 PM PDT 24
Finished Mar 10 01:12:48 PM PDT 24
Peak memory 203564 kb
Host smart-3eacbe06-83fe-4e3c-ab7a-bd14c4ed7897
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479144129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2479144129
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1609429403
Short name T283
Test name
Test status
Simulation time 31035909 ps
CPU time 0.66 seconds
Started Mar 10 01:12:47 PM PDT 24
Finished Mar 10 01:12:48 PM PDT 24
Peak memory 203372 kb
Host smart-51681e11-3e0c-46a7-8cb1-ab9a12bda95b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609429403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1609429403
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.4294342669
Short name T328
Test name
Test status
Simulation time 222488840 ps
CPU time 4.29 seconds
Started Mar 10 01:12:47 PM PDT 24
Finished Mar 10 01:12:51 PM PDT 24
Peak memory 203848 kb
Host smart-fdc0345c-3578-4c51-ac62-b5b5fd9cc004
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294342669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.4294342669
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.635866963
Short name T261
Test name
Test status
Simulation time 118044191 ps
CPU time 2.29 seconds
Started Mar 10 01:12:54 PM PDT 24
Finished Mar 10 01:12:58 PM PDT 24
Peak memory 203952 kb
Host smart-b9ec493e-c7a9-46b0-ab21-8d06d9619abd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635866963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.635866963
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1512058477
Short name T132
Test name
Test status
Simulation time 681512477 ps
CPU time 8.18 seconds
Started Mar 10 01:12:51 PM PDT 24
Finished Mar 10 01:12:59 PM PDT 24
Peak memory 212028 kb
Host smart-1a71bb0d-cc96-4d12-b65f-b2f0d6301d97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512058477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1512058477
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.3642899198
Short name T299
Test name
Test status
Simulation time 13822294877 ps
CPU time 43.08 seconds
Started Mar 10 01:13:15 PM PDT 24
Finished Mar 10 01:13:59 PM PDT 24
Peak memory 224904 kb
Host smart-8c4253c3-9fd2-459c-b0c5-0fe215e143cb
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642899198 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 22.rv_dm_tap_fsm_rand_reset.3642899198
Directory /workspace/22.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.3386831531
Short name T78
Test name
Test status
Simulation time 5004786303 ps
CPU time 19 seconds
Started Mar 10 01:13:09 PM PDT 24
Finished Mar 10 01:13:29 PM PDT 24
Peak memory 220308 kb
Host smart-15e07b36-d2c0-4ecb-8cf9-401940bc17f5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386831531 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 24.rv_dm_tap_fsm_rand_reset.3386831531
Directory /workspace/24.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.3538632501
Short name T320
Test name
Test status
Simulation time 12186311701 ps
CPU time 37.45 seconds
Started Mar 10 01:13:11 PM PDT 24
Finished Mar 10 01:13:50 PM PDT 24
Peak memory 220232 kb
Host smart-6e81bbd7-7be4-4f96-97f8-0976e02e5dca
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538632501 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 27.rv_dm_tap_fsm_rand_reset.3538632501
Directory /workspace/27.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1127217853
Short name T112
Test name
Test status
Simulation time 10757773660 ps
CPU time 67.84 seconds
Started Mar 10 01:12:51 PM PDT 24
Finished Mar 10 01:13:59 PM PDT 24
Peak memory 203040 kb
Host smart-52cbfb4f-78fb-4295-825d-f0e6d9677c9b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127217853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1127217853
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1282778767
Short name T334
Test name
Test status
Simulation time 119425417 ps
CPU time 2.39 seconds
Started Mar 10 01:12:48 PM PDT 24
Finished Mar 10 01:12:51 PM PDT 24
Peak memory 203772 kb
Host smart-f49a2124-9673-43d4-953b-99598a900259
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282778767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1282778767
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.4020986516
Short name T251
Test name
Test status
Simulation time 3500246745 ps
CPU time 5.66 seconds
Started Mar 10 01:12:53 PM PDT 24
Finished Mar 10 01:13:00 PM PDT 24
Peak memory 215352 kb
Host smart-ef1718c3-20f6-4250-8fa6-7ab514c4ac9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020986516 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.4020986516
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2628488789
Short name T110
Test name
Test status
Simulation time 382768573 ps
CPU time 2.32 seconds
Started Mar 10 01:12:49 PM PDT 24
Finished Mar 10 01:12:52 PM PDT 24
Peak memory 212020 kb
Host smart-c83b807b-2ecc-4f8e-9887-d8ee02af9a65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628488789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2628488789
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.307030707
Short name T365
Test name
Test status
Simulation time 10620950601 ps
CPU time 12.04 seconds
Started Mar 10 01:12:59 PM PDT 24
Finished Mar 10 01:13:12 PM PDT 24
Peak memory 203752 kb
Host smart-914e33c2-2c2e-44ff-9a63-09ce483a0c34
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307030707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_aliasing.307030707
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.4005663484
Short name T242
Test name
Test status
Simulation time 10211044791 ps
CPU time 30.34 seconds
Started Mar 10 01:12:50 PM PDT 24
Finished Mar 10 01:13:21 PM PDT 24
Peak memory 203700 kb
Host smart-ce2de3a0-8bb3-4b09-9ed4-decb69039f01
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005663484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.4005663484
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.44643166
Short name T99
Test name
Test status
Simulation time 358551929 ps
CPU time 1.6 seconds
Started Mar 10 01:12:59 PM PDT 24
Finished Mar 10 01:13:02 PM PDT 24
Peak memory 203688 kb
Host smart-14196dab-0fef-492d-b684-5a70314c5c74
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44643166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_
hw_reset.44643166
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3469862633
Short name T303
Test name
Test status
Simulation time 939409096 ps
CPU time 1.25 seconds
Started Mar 10 01:12:50 PM PDT 24
Finished Mar 10 01:12:52 PM PDT 24
Peak memory 203624 kb
Host smart-d121b1a1-f085-4707-96b1-9464ce60b809
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469862633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
469862633
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.341781499
Short name T279
Test name
Test status
Simulation time 198897922 ps
CPU time 1.02 seconds
Started Mar 10 01:12:52 PM PDT 24
Finished Mar 10 01:12:53 PM PDT 24
Peak memory 203536 kb
Host smart-6a581555-ad7e-41ea-a1fa-5cf9f443171d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341781499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_aliasing.341781499
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2885899118
Short name T311
Test name
Test status
Simulation time 2449896145 ps
CPU time 5.45 seconds
Started Mar 10 01:12:54 PM PDT 24
Finished Mar 10 01:13:01 PM PDT 24
Peak memory 203732 kb
Host smart-82557dca-96cb-4fac-8c1d-40548bd6d941
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885899118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2885899118
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1983565965
Short name T262
Test name
Test status
Simulation time 97725752 ps
CPU time 0.73 seconds
Started Mar 10 01:12:55 PM PDT 24
Finished Mar 10 01:12:57 PM PDT 24
Peak memory 203520 kb
Host smart-6cc82ae6-ae73-46fc-a6cb-e8748e2a95d4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983565965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.1983565965
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3693061760
Short name T259
Test name
Test status
Simulation time 57829774 ps
CPU time 0.81 seconds
Started Mar 10 01:12:44 PM PDT 24
Finished Mar 10 01:12:45 PM PDT 24
Peak memory 203476 kb
Host smart-20bb7586-6a78-4620-ba81-3daf9f661738
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693061760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3
693061760
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1181493325
Short name T247
Test name
Test status
Simulation time 22170471 ps
CPU time 0.64 seconds
Started Mar 10 01:12:50 PM PDT 24
Finished Mar 10 01:12:50 PM PDT 24
Peak memory 203548 kb
Host smart-3f5162b3-60b5-4a90-a252-57eb7d863d24
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181493325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.1181493325
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2185126898
Short name T337
Test name
Test status
Simulation time 90121204 ps
CPU time 0.65 seconds
Started Mar 10 01:12:53 PM PDT 24
Finished Mar 10 01:12:55 PM PDT 24
Peak memory 203472 kb
Host smart-f4138b4c-50ec-4202-98e5-e1da522bdef7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185126898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2185126898
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2370081372
Short name T103
Test name
Test status
Simulation time 302303727 ps
CPU time 3.65 seconds
Started Mar 10 01:12:51 PM PDT 24
Finished Mar 10 01:12:55 PM PDT 24
Peak memory 203828 kb
Host smart-e7f43472-11eb-4473-b298-b50e23e190e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370081372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.2370081372
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4181646339
Short name T339
Test name
Test status
Simulation time 246317596 ps
CPU time 2.9 seconds
Started Mar 10 01:12:54 PM PDT 24
Finished Mar 10 01:12:58 PM PDT 24
Peak memory 203892 kb
Host smart-e090a7c4-f4d0-4083-9b86-c9c1a2c26d64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181646339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.4181646339
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.519259414
Short name T309
Test name
Test status
Simulation time 2109529163 ps
CPU time 18.09 seconds
Started Mar 10 01:12:50 PM PDT 24
Finished Mar 10 01:13:08 PM PDT 24
Peak memory 214408 kb
Host smart-5fe73833-4b81-4b28-b713-bc107e1c266a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519259414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.519259414
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_dm_tap_fsm_rand_reset.482169323
Short name T136
Test name
Test status
Simulation time 23187141827 ps
CPU time 21.99 seconds
Started Mar 10 01:13:19 PM PDT 24
Finished Mar 10 01:13:41 PM PDT 24
Peak memory 220244 kb
Host smart-3e58806c-7285-49d9-9af3-609bc0e63c47
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482169323 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 30.rv_dm_tap_fsm_rand_reset.482169323
Directory /workspace/30.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.1212847314
Short name T340
Test name
Test status
Simulation time 24214515848 ps
CPU time 14.2 seconds
Started Mar 10 01:13:12 PM PDT 24
Finished Mar 10 01:13:27 PM PDT 24
Peak memory 217332 kb
Host smart-c3cc3ca0-b6ca-464b-ad4d-9cfea34d52e4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212847314 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 32.rv_dm_tap_fsm_rand_reset.1212847314
Directory /workspace/32.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.3270881043
Short name T264
Test name
Test status
Simulation time 8209549378 ps
CPU time 15.46 seconds
Started Mar 10 01:13:08 PM PDT 24
Finished Mar 10 01:13:24 PM PDT 24
Peak memory 220248 kb
Host smart-e9d9c01d-1f6d-4c27-853b-e36677cc7ac9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270881043 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 36.rv_dm_tap_fsm_rand_reset.3270881043
Directory /workspace/36.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3078550640
Short name T111
Test name
Test status
Simulation time 3370082784 ps
CPU time 29.38 seconds
Started Mar 10 01:12:51 PM PDT 24
Finished Mar 10 01:13:21 PM PDT 24
Peak memory 203776 kb
Host smart-11306333-3322-4b7b-a61d-37f60339c1cc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078550640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.3078550640
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4232414752
Short name T343
Test name
Test status
Simulation time 14718283063 ps
CPU time 67.59 seconds
Started Mar 10 01:12:54 PM PDT 24
Finished Mar 10 01:14:03 PM PDT 24
Peak memory 203716 kb
Host smart-74a40a3e-2a2e-43c2-9dbe-6f85dd096133
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232414752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.4232414752
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2482107096
Short name T371
Test name
Test status
Simulation time 419957080 ps
CPU time 2.4 seconds
Started Mar 10 01:12:51 PM PDT 24
Finished Mar 10 01:12:54 PM PDT 24
Peak memory 202968 kb
Host smart-b026e4b7-48b8-42fd-8352-9431d108603e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482107096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2482107096
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.4269091072
Short name T254
Test name
Test status
Simulation time 8693514388 ps
CPU time 9.43 seconds
Started Mar 10 01:12:54 PM PDT 24
Finished Mar 10 01:13:05 PM PDT 24
Peak memory 217000 kb
Host smart-64031add-488a-4337-a4e9-d2ea520e6d02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269091072 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.4269091072
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2012997594
Short name T270
Test name
Test status
Simulation time 135745497 ps
CPU time 2.04 seconds
Started Mar 10 01:12:54 PM PDT 24
Finished Mar 10 01:12:57 PM PDT 24
Peak memory 211948 kb
Host smart-a47c7813-fdf5-4ebf-a70a-f0e9dadf90cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012997594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2012997594
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1728299202
Short name T344
Test name
Test status
Simulation time 6542187751 ps
CPU time 10.09 seconds
Started Mar 10 01:12:51 PM PDT 24
Finished Mar 10 01:13:02 PM PDT 24
Peak memory 203608 kb
Host smart-09a4119f-f4ef-4f4f-9a25-77340f32b1db
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728299202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.1728299202
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2198828155
Short name T310
Test name
Test status
Simulation time 27107026351 ps
CPU time 50.26 seconds
Started Mar 10 01:12:59 PM PDT 24
Finished Mar 10 01:13:50 PM PDT 24
Peak memory 203744 kb
Host smart-d8ef997c-8b65-4cca-8879-ca573bfa99ab
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198828155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.2198828155
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.105370080
Short name T97
Test name
Test status
Simulation time 1292601564 ps
CPU time 4.58 seconds
Started Mar 10 01:12:53 PM PDT 24
Finished Mar 10 01:13:00 PM PDT 24
Peak memory 203744 kb
Host smart-b598541b-b8d2-4e25-a8fd-0c2a208d3e52
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105370080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_hw_reset.105370080
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2015116812
Short name T325
Test name
Test status
Simulation time 319128657 ps
CPU time 1.36 seconds
Started Mar 10 01:12:51 PM PDT 24
Finished Mar 10 01:12:52 PM PDT 24
Peak memory 203628 kb
Host smart-fc6edf9b-352d-4ccd-99e7-4f01c4307a5c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015116812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2
015116812
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1034501553
Short name T278
Test name
Test status
Simulation time 304007873 ps
CPU time 0.94 seconds
Started Mar 10 01:12:50 PM PDT 24
Finished Mar 10 01:12:51 PM PDT 24
Peak memory 203544 kb
Host smart-12d396df-9777-424d-b6fa-ab2914823e49
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034501553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.1034501553
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3955410
Short name T272
Test name
Test status
Simulation time 2436389913 ps
CPU time 5.29 seconds
Started Mar 10 01:12:50 PM PDT 24
Finished Mar 10 01:12:56 PM PDT 24
Peak memory 203824 kb
Host smart-5a7739fd-c52a-4f24-a6c1-02caf6707e09
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_b
it_bash.3955410
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3773343040
Short name T275
Test name
Test status
Simulation time 84211481 ps
CPU time 0.68 seconds
Started Mar 10 01:12:50 PM PDT 24
Finished Mar 10 01:12:51 PM PDT 24
Peak memory 203384 kb
Host smart-ca1bc258-a2e9-4b75-877b-ad0fac57533d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773343040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.3773343040
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2602742888
Short name T315
Test name
Test status
Simulation time 171410848 ps
CPU time 0.78 seconds
Started Mar 10 01:12:49 PM PDT 24
Finished Mar 10 01:12:50 PM PDT 24
Peak memory 203464 kb
Host smart-7c03f532-42ae-4c68-9168-18b6e709ec9e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602742888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
602742888
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2317248811
Short name T266
Test name
Test status
Simulation time 36470692 ps
CPU time 0.67 seconds
Started Mar 10 01:12:53 PM PDT 24
Finished Mar 10 01:12:55 PM PDT 24
Peak memory 203536 kb
Host smart-373eb80a-0c28-4139-a32e-413a984e588d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317248811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.2317248811
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.245217256
Short name T306
Test name
Test status
Simulation time 25458095 ps
CPU time 0.66 seconds
Started Mar 10 01:12:54 PM PDT 24
Finished Mar 10 01:12:56 PM PDT 24
Peak memory 203436 kb
Host smart-d803d81c-9bdd-4049-8ba3-96c1f1b44a93
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245217256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.245217256
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.173774284
Short name T90
Test name
Test status
Simulation time 1150397337 ps
CPU time 4.29 seconds
Started Mar 10 01:12:53 PM PDT 24
Finished Mar 10 01:12:59 PM PDT 24
Peak memory 203812 kb
Host smart-15e63e3b-a740-4fcc-994b-4925aff37756
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173774284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c
sr_outstanding.173774284
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.571762549
Short name T280
Test name
Test status
Simulation time 7403486444 ps
CPU time 14.57 seconds
Started Mar 10 01:12:59 PM PDT 24
Finished Mar 10 01:13:15 PM PDT 24
Peak memory 220264 kb
Host smart-467a96a3-1de6-4431-9934-6969193aca4d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571762549 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.571762549
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1341322093
Short name T263
Test name
Test status
Simulation time 152550738 ps
CPU time 3.95 seconds
Started Mar 10 01:12:53 PM PDT 24
Finished Mar 10 01:12:59 PM PDT 24
Peak memory 203940 kb
Host smart-77895304-2497-4487-87ee-9fa14fe9154b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341322093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1341322093
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.4155152133
Short name T83
Test name
Test status
Simulation time 600797213 ps
CPU time 15.6 seconds
Started Mar 10 01:12:50 PM PDT 24
Finished Mar 10 01:13:06 PM PDT 24
Peak memory 212260 kb
Host smart-cb7bb1f5-3d32-4f41-ba7d-ffc0441806f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155152133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.4155152133
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3795005472
Short name T281
Test name
Test status
Simulation time 336678581 ps
CPU time 2.16 seconds
Started Mar 10 01:12:53 PM PDT 24
Finished Mar 10 01:12:56 PM PDT 24
Peak memory 220192 kb
Host smart-1424a8b1-4d4d-4746-87af-b8eda58b486a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795005472 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3795005472
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1196906345
Short name T257
Test name
Test status
Simulation time 96263171 ps
CPU time 1.57 seconds
Started Mar 10 01:12:55 PM PDT 24
Finished Mar 10 01:12:57 PM PDT 24
Peak memory 211932 kb
Host smart-43efa097-67a1-4d9e-87d4-fb23ee814305
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196906345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1196906345
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.883414365
Short name T368
Test name
Test status
Simulation time 844809827 ps
CPU time 3.33 seconds
Started Mar 10 01:12:53 PM PDT 24
Finished Mar 10 01:12:58 PM PDT 24
Peak memory 203676 kb
Host smart-61b5a529-30be-43ef-be84-764cc1101a26
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883414365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.883414365
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.4121507836
Short name T357
Test name
Test status
Simulation time 47360119 ps
CPU time 0.7 seconds
Started Mar 10 01:12:54 PM PDT 24
Finished Mar 10 01:12:56 PM PDT 24
Peak memory 203468 kb
Host smart-07fc78f1-3f5d-4e03-8942-579a2ca50aec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121507836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.4
121507836
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2852332293
Short name T349
Test name
Test status
Simulation time 1331199000 ps
CPU time 6.66 seconds
Started Mar 10 01:12:53 PM PDT 24
Finished Mar 10 01:13:01 PM PDT 24
Peak memory 203808 kb
Host smart-5c4ee801-338a-4309-879f-9081c2d6e66f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852332293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2852332293
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2270409409
Short name T133
Test name
Test status
Simulation time 299234059 ps
CPU time 8.09 seconds
Started Mar 10 01:12:53 PM PDT 24
Finished Mar 10 01:13:02 PM PDT 24
Peak memory 212072 kb
Host smart-203742d0-bec2-4d73-b4b9-45fea770dc80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270409409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2270409409
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1746920571
Short name T258
Test name
Test status
Simulation time 138258543 ps
CPU time 2.26 seconds
Started Mar 10 01:12:58 PM PDT 24
Finished Mar 10 01:13:01 PM PDT 24
Peak memory 214640 kb
Host smart-ef88ce58-26ee-4df3-8239-1f85eb25059b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746920571 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1746920571
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2643504723
Short name T116
Test name
Test status
Simulation time 35308448 ps
CPU time 1.43 seconds
Started Mar 10 01:12:58 PM PDT 24
Finished Mar 10 01:13:00 PM PDT 24
Peak memory 203760 kb
Host smart-518e260a-12dc-4adf-b3ae-2578b9863c13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643504723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2643504723
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3363861831
Short name T317
Test name
Test status
Simulation time 451546981 ps
CPU time 1.65 seconds
Started Mar 10 01:12:59 PM PDT 24
Finished Mar 10 01:13:01 PM PDT 24
Peak memory 203676 kb
Host smart-214a7c76-c766-4ae4-8b8e-d0ccc8add3fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363861831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
363861831
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1018620006
Short name T79
Test name
Test status
Simulation time 59847005 ps
CPU time 0.66 seconds
Started Mar 10 01:12:53 PM PDT 24
Finished Mar 10 01:12:55 PM PDT 24
Peak memory 203464 kb
Host smart-441dc414-7c9a-4d10-9224-8da1d8989ad8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018620006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
018620006
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2575039795
Short name T66
Test name
Test status
Simulation time 389246841 ps
CPU time 7.08 seconds
Started Mar 10 01:12:54 PM PDT 24
Finished Mar 10 01:13:02 PM PDT 24
Peak memory 203888 kb
Host smart-34e4b2c1-04cd-4e2b-b9f2-5c49f865a264
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575039795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2575039795
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2412512574
Short name T82
Test name
Test status
Simulation time 63301906 ps
CPU time 2.25 seconds
Started Mar 10 01:12:50 PM PDT 24
Finished Mar 10 01:12:52 PM PDT 24
Peak memory 212116 kb
Host smart-33992735-2cd7-41a1-b3fa-aa1d3c7c175b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412512574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2412512574
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2609699653
Short name T84
Test name
Test status
Simulation time 4870933165 ps
CPU time 16.18 seconds
Started Mar 10 01:12:54 PM PDT 24
Finished Mar 10 01:13:11 PM PDT 24
Peak memory 212720 kb
Host smart-b10ef7cb-57d5-41de-9b8a-2f5744cdd9b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609699653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2609699653
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1132196204
Short name T331
Test name
Test status
Simulation time 1071679685 ps
CPU time 2.66 seconds
Started Mar 10 01:12:55 PM PDT 24
Finished Mar 10 01:12:59 PM PDT 24
Peak memory 212096 kb
Host smart-63327772-acea-48b9-89fd-429d824a5442
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132196204 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1132196204
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3859732394
Short name T88
Test name
Test status
Simulation time 757572013 ps
CPU time 1.6 seconds
Started Mar 10 01:12:56 PM PDT 24
Finished Mar 10 01:12:59 PM PDT 24
Peak memory 203676 kb
Host smart-3ae8e0a3-9021-4b48-b312-e81ff9f8578e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859732394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3859732394
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3036185122
Short name T345
Test name
Test status
Simulation time 165674646 ps
CPU time 1.04 seconds
Started Mar 10 01:12:54 PM PDT 24
Finished Mar 10 01:12:56 PM PDT 24
Peak memory 203616 kb
Host smart-9d25f734-15e0-4646-976c-0e89fe0aad70
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036185122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3
036185122
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1799253269
Short name T353
Test name
Test status
Simulation time 118233253 ps
CPU time 0.67 seconds
Started Mar 10 01:12:55 PM PDT 24
Finished Mar 10 01:12:57 PM PDT 24
Peak memory 203500 kb
Host smart-ec8caccf-db9c-4560-a996-95ff5683bf7e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799253269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
799253269
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2195756859
Short name T106
Test name
Test status
Simulation time 226099564 ps
CPU time 4.05 seconds
Started Mar 10 01:12:57 PM PDT 24
Finished Mar 10 01:13:02 PM PDT 24
Peak memory 203776 kb
Host smart-8a7fb708-fbc5-4b97-9de9-87d6639ee349
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195756859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.2195756859
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2150934617
Short name T50
Test name
Test status
Simulation time 476982459 ps
CPU time 2.89 seconds
Started Mar 10 01:12:56 PM PDT 24
Finished Mar 10 01:13:00 PM PDT 24
Peak memory 203780 kb
Host smart-a5edc0a6-7f07-4bf0-a101-36a0103076b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150934617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2150934617
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3888793536
Short name T126
Test name
Test status
Simulation time 1554905100 ps
CPU time 16.03 seconds
Started Mar 10 01:12:57 PM PDT 24
Finished Mar 10 01:13:14 PM PDT 24
Peak memory 212024 kb
Host smart-f0d2d71d-0c31-4571-9f1a-f070a6a85a68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888793536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3888793536
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1133222933
Short name T292
Test name
Test status
Simulation time 4728107370 ps
CPU time 5.57 seconds
Started Mar 10 01:12:54 PM PDT 24
Finished Mar 10 01:13:01 PM PDT 24
Peak memory 220324 kb
Host smart-a37b4779-aebd-4f7c-9d73-3cf8b20b92e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133222933 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1133222933
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2456765125
Short name T89
Test name
Test status
Simulation time 90686447 ps
CPU time 1.36 seconds
Started Mar 10 01:13:02 PM PDT 24
Finished Mar 10 01:13:04 PM PDT 24
Peak memory 203724 kb
Host smart-1f01c57a-1af8-4114-b3d6-2cb539e39479
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456765125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2456765125
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1567284463
Short name T308
Test name
Test status
Simulation time 237147063 ps
CPU time 0.94 seconds
Started Mar 10 01:12:56 PM PDT 24
Finished Mar 10 01:12:58 PM PDT 24
Peak memory 203744 kb
Host smart-1a0a6ba6-e0e8-42b6-beb4-f92bbadee1b0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567284463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
567284463
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2051843641
Short name T302
Test name
Test status
Simulation time 53425023 ps
CPU time 0.63 seconds
Started Mar 10 01:12:56 PM PDT 24
Finished Mar 10 01:12:57 PM PDT 24
Peak memory 203540 kb
Host smart-94121130-b570-44e2-b817-1799eba54e58
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051843641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
051843641
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.497365826
Short name T105
Test name
Test status
Simulation time 432169107 ps
CPU time 4.08 seconds
Started Mar 10 01:12:54 PM PDT 24
Finished Mar 10 01:12:59 PM PDT 24
Peak memory 203808 kb
Host smart-22b338e0-507b-45c8-819e-0f80c972e381
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497365826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.497365826
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2356880879
Short name T267
Test name
Test status
Simulation time 83647937 ps
CPU time 2.24 seconds
Started Mar 10 01:12:56 PM PDT 24
Finished Mar 10 01:12:59 PM PDT 24
Peak memory 203892 kb
Host smart-e230061c-e640-4805-a55d-6ff5168bdfc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356880879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2356880879
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3896393132
Short name T161
Test name
Test status
Simulation time 3452095262 ps
CPU time 3.37 seconds
Started Mar 10 01:13:05 PM PDT 24
Finished Mar 10 01:13:09 PM PDT 24
Peak memory 212132 kb
Host smart-95af3cc8-aedc-4e7d-8f49-8573c3aa70a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896393132 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3896393132
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2733683248
Short name T117
Test name
Test status
Simulation time 284709471 ps
CPU time 1.5 seconds
Started Mar 10 01:12:59 PM PDT 24
Finished Mar 10 01:13:01 PM PDT 24
Peak memory 203700 kb
Host smart-f0013026-2a46-452d-b324-8e2efe2eb33e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733683248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2733683248
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.756866308
Short name T252
Test name
Test status
Simulation time 675709002 ps
CPU time 1.21 seconds
Started Mar 10 01:12:55 PM PDT 24
Finished Mar 10 01:12:58 PM PDT 24
Peak memory 203776 kb
Host smart-0e85484c-38e7-41bb-8922-95805b42f361
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756866308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.756866308
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.309032058
Short name T244
Test name
Test status
Simulation time 76292467 ps
CPU time 0.71 seconds
Started Mar 10 01:12:57 PM PDT 24
Finished Mar 10 01:12:58 PM PDT 24
Peak memory 203472 kb
Host smart-1d31b7ef-8533-40e4-96ee-254472999486
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309032058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.309032058
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1193310536
Short name T102
Test name
Test status
Simulation time 1388469844 ps
CPU time 4.61 seconds
Started Mar 10 01:13:00 PM PDT 24
Finished Mar 10 01:13:05 PM PDT 24
Peak memory 203896 kb
Host smart-3bfee6f2-5767-4f3e-b6d9-14af87ecf52c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193310536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.1193310536
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1518011977
Short name T330
Test name
Test status
Simulation time 4839087454 ps
CPU time 5.88 seconds
Started Mar 10 01:12:57 PM PDT 24
Finished Mar 10 01:13:03 PM PDT 24
Peak memory 212152 kb
Host smart-d6458055-6b03-4229-8acd-ec0d3fb8ee96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518011977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1518011977
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3566841087
Short name T130
Test name
Test status
Simulation time 1709962743 ps
CPU time 18.43 seconds
Started Mar 10 01:12:56 PM PDT 24
Finished Mar 10 01:13:15 PM PDT 24
Peak memory 215032 kb
Host smart-9853c3d7-4e51-45d9-898f-1f2a731eab11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566841087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3566841087
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.2089591645
Short name T199
Test name
Test status
Simulation time 4230345706 ps
CPU time 16.14 seconds
Started Mar 10 01:09:58 PM PDT 24
Finished Mar 10 01:10:15 PM PDT 24
Peak memory 203836 kb
Host smart-16bb69bb-ec77-4536-bfae-2bc6f9a5bab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089591645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2089591645
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.3743204480
Short name T12
Test name
Test status
Simulation time 968589381 ps
CPU time 3.87 seconds
Started Mar 10 01:09:56 PM PDT 24
Finished Mar 10 01:10:00 PM PDT 24
Peak memory 203484 kb
Host smart-62bd56f7-893b-4a34-8768-a64e3c512781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743204480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3743204480
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2524362676
Short name T137
Test name
Test status
Simulation time 1279487534 ps
CPU time 4.64 seconds
Started Mar 10 01:09:56 PM PDT 24
Finished Mar 10 01:10:01 PM PDT 24
Peak memory 203516 kb
Host smart-0583c2a1-87a6-4078-9721-01fda54fc9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524362676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2524362676
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.27660932
Short name T235
Test name
Test status
Simulation time 48644826 ps
CPU time 0.76 seconds
Started Mar 10 01:09:57 PM PDT 24
Finished Mar 10 01:09:58 PM PDT 24
Peak memory 203148 kb
Host smart-843fb1c6-dd71-4def-ad98-d428b9946135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27660932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.27660932
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.4259795004
Short name T205
Test name
Test status
Simulation time 5625790758 ps
CPU time 9.13 seconds
Started Mar 10 01:10:01 PM PDT 24
Finished Mar 10 01:10:10 PM PDT 24
Peak memory 203728 kb
Host smart-9fc4b2cf-9f4d-4987-9b82-56afe930044f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4259795004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.4259795004
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.3500617329
Short name T35
Test name
Test status
Simulation time 171056467 ps
CPU time 1.39 seconds
Started Mar 10 01:09:57 PM PDT 24
Finished Mar 10 01:09:59 PM PDT 24
Peak memory 203620 kb
Host smart-a0df8b71-a71f-47f5-a4e9-c725afa49b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500617329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3500617329
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.2266617916
Short name T11
Test name
Test status
Simulation time 24515282 ps
CPU time 0.67 seconds
Started Mar 10 01:09:59 PM PDT 24
Finished Mar 10 01:10:00 PM PDT 24
Peak memory 203292 kb
Host smart-49c71d69-5f4f-48db-8677-db91f64020a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266617916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.2266617916
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2987359200
Short name T17
Test name
Test status
Simulation time 185609540 ps
CPU time 0.78 seconds
Started Mar 10 01:09:58 PM PDT 24
Finished Mar 10 01:10:00 PM PDT 24
Peak memory 203296 kb
Host smart-e648aa83-fb8b-421c-a6fb-07a4091f3e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987359200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2987359200
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2839942790
Short name T213
Test name
Test status
Simulation time 472419811 ps
CPU time 1.02 seconds
Started Mar 10 01:09:57 PM PDT 24
Finished Mar 10 01:09:59 PM PDT 24
Peak memory 203280 kb
Host smart-867d044e-7d75-4ab4-b00d-5eae6e18786e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839942790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2839942790
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.470186448
Short name T10
Test name
Test status
Simulation time 30768731 ps
CPU time 0.66 seconds
Started Mar 10 01:09:56 PM PDT 24
Finished Mar 10 01:09:57 PM PDT 24
Peak memory 203108 kb
Host smart-0c262fb0-fffd-40a1-9875-262287d6c731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470186448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.470186448
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2831988119
Short name T139
Test name
Test status
Simulation time 79958640 ps
CPU time 0.72 seconds
Started Mar 10 01:09:56 PM PDT 24
Finished Mar 10 01:09:57 PM PDT 24
Peak memory 203372 kb
Host smart-f856a32c-c9f7-46a1-92a9-74622d5b6318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831988119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2831988119
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1847399835
Short name T15
Test name
Test status
Simulation time 497489991 ps
CPU time 1.51 seconds
Started Mar 10 01:09:58 PM PDT 24
Finished Mar 10 01:10:00 PM PDT 24
Peak memory 203500 kb
Host smart-62671415-802e-48df-87c6-0c541eba1ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847399835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1847399835
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.1920572202
Short name T138
Test name
Test status
Simulation time 388069173 ps
CPU time 1.84 seconds
Started Mar 10 01:09:59 PM PDT 24
Finished Mar 10 01:10:01 PM PDT 24
Peak memory 203252 kb
Host smart-412d9768-9c46-415e-b77d-365a2886c06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920572202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1920572202
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.2692764162
Short name T34
Test name
Test status
Simulation time 555188094 ps
CPU time 1.07 seconds
Started Mar 10 01:09:59 PM PDT 24
Finished Mar 10 01:10:01 PM PDT 24
Peak memory 203520 kb
Host smart-b630ce3c-ab53-4789-a67e-713a0ec04156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692764162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.2692764162
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.910139410
Short name T218
Test name
Test status
Simulation time 13449006378 ps
CPU time 43.71 seconds
Started Mar 10 01:09:59 PM PDT 24
Finished Mar 10 01:10:43 PM PDT 24
Peak memory 203852 kb
Host smart-73e03222-101c-428f-923e-1c362481f420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910139410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.910139410
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3542236040
Short name T46
Test name
Test status
Simulation time 116285922 ps
CPU time 0.97 seconds
Started Mar 10 01:09:56 PM PDT 24
Finished Mar 10 01:09:58 PM PDT 24
Peak memory 218248 kb
Host smart-3127eaa9-6dcd-4e28-a53f-f21add55bc4c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542236040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3542236040
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.505401829
Short name T28
Test name
Test status
Simulation time 465203354 ps
CPU time 2.06 seconds
Started Mar 10 01:09:57 PM PDT 24
Finished Mar 10 01:10:00 PM PDT 24
Peak memory 202980 kb
Host smart-01e4bf41-d3a0-4530-9d0d-0ba168ae6271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505401829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.505401829
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.1476438345
Short name T160
Test name
Test status
Simulation time 20237027 ps
CPU time 0.67 seconds
Started Mar 10 01:10:04 PM PDT 24
Finished Mar 10 01:10:05 PM PDT 24
Peak memory 203412 kb
Host smart-6bf11cf5-b357-44b9-b689-17cbd14bb2a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476438345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1476438345
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2740364128
Short name T200
Test name
Test status
Simulation time 9161558410 ps
CPU time 9.42 seconds
Started Mar 10 01:10:03 PM PDT 24
Finished Mar 10 01:10:13 PM PDT 24
Peak memory 203708 kb
Host smart-5503236d-1d20-4163-a3f0-25f86e6a2f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740364128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2740364128
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.24215738
Short name T13
Test name
Test status
Simulation time 1458155529 ps
CPU time 3 seconds
Started Mar 10 01:10:10 PM PDT 24
Finished Mar 10 01:10:14 PM PDT 24
Peak memory 203536 kb
Host smart-3ba7f7f5-6658-41e0-b6d9-85e8dbfca4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24215738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.24215738
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.995400558
Short name T29
Test name
Test status
Simulation time 155204907 ps
CPU time 0.73 seconds
Started Mar 10 01:10:06 PM PDT 24
Finished Mar 10 01:10:07 PM PDT 24
Peak memory 203068 kb
Host smart-17cad4f3-fa3c-4a88-9fdf-3641911566cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995400558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.995400558
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3227649118
Short name T26
Test name
Test status
Simulation time 2818993612 ps
CPU time 2.92 seconds
Started Mar 10 01:10:03 PM PDT 24
Finished Mar 10 01:10:06 PM PDT 24
Peak memory 203644 kb
Host smart-59621390-e6c4-412a-aea2-eb81509c4417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227649118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3227649118
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1663931804
Short name T27
Test name
Test status
Simulation time 44247450 ps
CPU time 0.7 seconds
Started Mar 10 01:10:04 PM PDT 24
Finished Mar 10 01:10:04 PM PDT 24
Peak memory 203300 kb
Host smart-fd78a7e6-d60c-4b1a-8386-ea0212dffdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663931804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1663931804
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2906649688
Short name T62
Test name
Test status
Simulation time 2232482871 ps
CPU time 6.19 seconds
Started Mar 10 01:10:03 PM PDT 24
Finished Mar 10 01:10:10 PM PDT 24
Peak memory 203796 kb
Host smart-a9785350-7287-4146-8ec7-a9f1efe63b6f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2906649688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2906649688
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2951024583
Short name T32
Test name
Test status
Simulation time 450945342 ps
CPU time 1.79 seconds
Started Mar 10 01:10:04 PM PDT 24
Finished Mar 10 01:10:06 PM PDT 24
Peak memory 203456 kb
Host smart-0cf6e36d-5acc-4f82-8469-79d31ba39be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951024583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2951024583
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.1595010190
Short name T176
Test name
Test status
Simulation time 70437441 ps
CPU time 0.76 seconds
Started Mar 10 01:10:04 PM PDT 24
Finished Mar 10 01:10:05 PM PDT 24
Peak memory 203256 kb
Host smart-1fc6c6a1-2944-4571-97b3-c670f64b7ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595010190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1595010190
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1457280932
Short name T216
Test name
Test status
Simulation time 98946892 ps
CPU time 0.76 seconds
Started Mar 10 01:10:04 PM PDT 24
Finished Mar 10 01:10:05 PM PDT 24
Peak memory 203268 kb
Host smart-d6429f67-6e6b-40fa-8bba-c70499234b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457280932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1457280932
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1914679785
Short name T18
Test name
Test status
Simulation time 156890893 ps
CPU time 1.29 seconds
Started Mar 10 01:10:04 PM PDT 24
Finished Mar 10 01:10:06 PM PDT 24
Peak memory 203436 kb
Host smart-63d1f631-9973-47b3-ac3f-5d2b5994d112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914679785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1914679785
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.596116119
Short name T24
Test name
Test status
Simulation time 67945928 ps
CPU time 0.8 seconds
Started Mar 10 01:10:03 PM PDT 24
Finished Mar 10 01:10:04 PM PDT 24
Peak memory 203304 kb
Host smart-3ce2c7de-b2fc-4053-b541-f4e4d316a9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596116119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.596116119
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1561577256
Short name T8
Test name
Test status
Simulation time 91544758 ps
CPU time 0.71 seconds
Started Mar 10 01:10:04 PM PDT 24
Finished Mar 10 01:10:05 PM PDT 24
Peak memory 203380 kb
Host smart-c9a064ba-2f6a-4a7f-a283-9381df96030a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561577256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1561577256
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.30233144
Short name T14
Test name
Test status
Simulation time 446767942 ps
CPU time 1.1 seconds
Started Mar 10 01:10:08 PM PDT 24
Finished Mar 10 01:10:09 PM PDT 24
Peak memory 203460 kb
Host smart-4df1179d-e6b9-4767-b2aa-dd6e66d77b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30233144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.30233144
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.3939996385
Short name T9
Test name
Test status
Simulation time 1183562048 ps
CPU time 4.18 seconds
Started Mar 10 01:10:10 PM PDT 24
Finished Mar 10 01:10:15 PM PDT 24
Peak memory 203576 kb
Host smart-c5c2cc72-bb9b-4a9a-85d9-60db9bb3630c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939996385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3939996385
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3493725716
Short name T31
Test name
Test status
Simulation time 57278465 ps
CPU time 0.74 seconds
Started Mar 10 01:10:10 PM PDT 24
Finished Mar 10 01:10:12 PM PDT 24
Peak memory 203408 kb
Host smart-5c53fcc6-0b10-48f3-b1d5-5c937ae76cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493725716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3493725716
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2700454643
Short name T197
Test name
Test status
Simulation time 8826293677 ps
CPU time 15.32 seconds
Started Mar 10 01:10:05 PM PDT 24
Finished Mar 10 01:10:21 PM PDT 24
Peak memory 203736 kb
Host smart-2e5ee4c8-bf5c-46ec-89fc-78e3655a569a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700454643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2700454643
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.3126703342
Short name T21
Test name
Test status
Simulation time 365630690 ps
CPU time 1.46 seconds
Started Mar 10 01:10:06 PM PDT 24
Finished Mar 10 01:10:08 PM PDT 24
Peak memory 203480 kb
Host smart-65f06da8-106b-4438-b6aa-7949cd37071b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126703342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3126703342
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.4218105520
Short name T210
Test name
Test status
Simulation time 58860282 ps
CPU time 0.69 seconds
Started Mar 10 01:10:15 PM PDT 24
Finished Mar 10 01:10:18 PM PDT 24
Peak memory 203432 kb
Host smart-f492a8f7-9f37-40f7-bab8-58e42da40a51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218105520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.4218105520
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.1912144446
Short name T64
Test name
Test status
Simulation time 650756214 ps
CPU time 1.63 seconds
Started Mar 10 01:10:19 PM PDT 24
Finished Mar 10 01:10:21 PM PDT 24
Peak memory 203628 kb
Host smart-c170e29c-f99b-4171-b56d-293e79aac68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912144446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1912144446
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3839962224
Short name T173
Test name
Test status
Simulation time 6055682461 ps
CPU time 25.18 seconds
Started Mar 10 01:10:15 PM PDT 24
Finished Mar 10 01:10:41 PM PDT 24
Peak memory 203704 kb
Host smart-89784408-0c6b-4219-b0b9-278df565f053
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3839962224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3839962224
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1635994841
Short name T220
Test name
Test status
Simulation time 840583462 ps
CPU time 4.45 seconds
Started Mar 10 01:10:18 PM PDT 24
Finished Mar 10 01:10:24 PM PDT 24
Peak memory 203620 kb
Host smart-fca15ca4-3049-4816-a0f2-b10b8652c4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635994841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1635994841
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.3934788005
Short name T174
Test name
Test status
Simulation time 26792638 ps
CPU time 0.66 seconds
Started Mar 10 01:10:19 PM PDT 24
Finished Mar 10 01:10:20 PM PDT 24
Peak memory 203428 kb
Host smart-4d52d252-db6c-4b00-a11e-ba12b02d9d3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934788005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3934788005
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.1359100572
Short name T124
Test name
Test status
Simulation time 1109507847 ps
CPU time 2.85 seconds
Started Mar 10 01:10:18 PM PDT 24
Finished Mar 10 01:10:22 PM PDT 24
Peak memory 203680 kb
Host smart-cf4c52a3-eed2-4758-9994-3e366f42d4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359100572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1359100572
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2204802111
Short name T230
Test name
Test status
Simulation time 1900652591 ps
CPU time 10.11 seconds
Started Mar 10 01:10:15 PM PDT 24
Finished Mar 10 01:10:27 PM PDT 24
Peak memory 203704 kb
Host smart-9d185317-45f4-417c-b314-69b55b25dfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204802111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2204802111
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2255225544
Short name T202
Test name
Test status
Simulation time 2849253298 ps
CPU time 7.22 seconds
Started Mar 10 01:10:14 PM PDT 24
Finished Mar 10 01:10:22 PM PDT 24
Peak memory 203776 kb
Host smart-067fd69e-8e61-4b4c-bae8-9c1612cf19f5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2255225544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.2255225544
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.3586793582
Short name T229
Test name
Test status
Simulation time 2073475974 ps
CPU time 6.18 seconds
Started Mar 10 01:10:20 PM PDT 24
Finished Mar 10 01:10:27 PM PDT 24
Peak memory 203700 kb
Host smart-8db5aa7c-8f69-4ce4-af44-1a5616d08b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586793582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3586793582
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2519885251
Short name T158
Test name
Test status
Simulation time 27697936 ps
CPU time 0.65 seconds
Started Mar 10 01:10:15 PM PDT 24
Finished Mar 10 01:10:18 PM PDT 24
Peak memory 203356 kb
Host smart-698c00ac-9806-49d0-8a61-86b5fa3c118b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519885251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2519885251
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.2750374405
Short name T2
Test name
Test status
Simulation time 3140878986 ps
CPU time 10.95 seconds
Started Mar 10 01:10:18 PM PDT 24
Finished Mar 10 01:10:30 PM PDT 24
Peak memory 203692 kb
Host smart-403a76df-ecd1-46ea-954f-34bcb5d58001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750374405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2750374405
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2684854638
Short name T185
Test name
Test status
Simulation time 1823866619 ps
CPU time 8.31 seconds
Started Mar 10 01:10:15 PM PDT 24
Finished Mar 10 01:10:25 PM PDT 24
Peak memory 203608 kb
Host smart-e8711859-1e56-4730-b5db-89a7a1a6aa32
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2684854638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.2684854638
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.185891634
Short name T234
Test name
Test status
Simulation time 1998835697 ps
CPU time 3.06 seconds
Started Mar 10 01:10:18 PM PDT 24
Finished Mar 10 01:10:22 PM PDT 24
Peak memory 203664 kb
Host smart-f4514910-4b9d-409c-b9d9-3d0a8c982157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185891634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.185891634
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3301022620
Short name T143
Test name
Test status
Simulation time 35608876 ps
CPU time 0.68 seconds
Started Mar 10 01:10:23 PM PDT 24
Finished Mar 10 01:10:24 PM PDT 24
Peak memory 203388 kb
Host smart-05263c11-91e9-4544-942f-c8a6c3ce627b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301022620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3301022620
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.3163880936
Short name T219
Test name
Test status
Simulation time 1029611370 ps
CPU time 2.04 seconds
Started Mar 10 01:10:15 PM PDT 24
Finished Mar 10 01:10:19 PM PDT 24
Peak memory 203660 kb
Host smart-fde02611-6bc7-4866-b026-7b6676248c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163880936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.3163880936
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1312383141
Short name T167
Test name
Test status
Simulation time 317580494 ps
CPU time 2.02 seconds
Started Mar 10 01:10:18 PM PDT 24
Finished Mar 10 01:10:21 PM PDT 24
Peak memory 203748 kb
Host smart-b9092130-b2c0-4b99-a01a-1d1e2c28cea2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1312383141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.1312383141
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.2924422184
Short name T204
Test name
Test status
Simulation time 2655501730 ps
CPU time 9.44 seconds
Started Mar 10 01:10:14 PM PDT 24
Finished Mar 10 01:10:25 PM PDT 24
Peak memory 203796 kb
Host smart-38f1e580-ce1a-4c41-a8f8-7c97ff37341d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924422184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.2924422184
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.3718445389
Short name T186
Test name
Test status
Simulation time 21161397141 ps
CPU time 82.05 seconds
Started Mar 10 01:10:24 PM PDT 24
Finished Mar 10 01:11:46 PM PDT 24
Peak memory 203732 kb
Host smart-c536e358-d258-48a9-b81a-f499b8455449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718445389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3718445389
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.1189724445
Short name T37
Test name
Test status
Simulation time 5606310886 ps
CPU time 8.3 seconds
Started Mar 10 01:10:26 PM PDT 24
Finished Mar 10 01:10:34 PM PDT 24
Peak memory 203736 kb
Host smart-8e9338eb-b57d-43e6-adc4-29626956757f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189724445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1189724445
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2366012752
Short name T179
Test name
Test status
Simulation time 3219510345 ps
CPU time 9.09 seconds
Started Mar 10 01:10:22 PM PDT 24
Finished Mar 10 01:10:32 PM PDT 24
Peak memory 203728 kb
Host smart-1b59428f-8cec-4cf0-8eb6-ff9b680aa26b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2366012752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.2366012752
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.1791952300
Short name T203
Test name
Test status
Simulation time 5214514584 ps
CPU time 6.55 seconds
Started Mar 10 01:10:23 PM PDT 24
Finished Mar 10 01:10:30 PM PDT 24
Peak memory 203848 kb
Host smart-1ace149f-3d47-4c95-8da8-89633789fd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791952300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1791952300
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.2647874181
Short name T146
Test name
Test status
Simulation time 29772861 ps
CPU time 0.64 seconds
Started Mar 10 01:10:25 PM PDT 24
Finished Mar 10 01:10:26 PM PDT 24
Peak memory 203404 kb
Host smart-907ddc60-6172-493a-96be-182003a76480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647874181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2647874181
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3213297291
Short name T23
Test name
Test status
Simulation time 31007095898 ps
CPU time 123.58 seconds
Started Mar 10 01:10:22 PM PDT 24
Finished Mar 10 01:12:25 PM PDT 24
Peak memory 203688 kb
Host smart-62d3bca2-198e-4c41-a82d-7d34ab8a4b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213297291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3213297291
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.4105119744
Short name T207
Test name
Test status
Simulation time 12600005132 ps
CPU time 26.25 seconds
Started Mar 10 01:10:25 PM PDT 24
Finished Mar 10 01:10:52 PM PDT 24
Peak memory 203736 kb
Host smart-5a5e6a19-6a28-41a7-99d8-89469a9a07b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105119744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.4105119744
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1262916940
Short name T223
Test name
Test status
Simulation time 1417536083 ps
CPU time 4.61 seconds
Started Mar 10 01:10:22 PM PDT 24
Finished Mar 10 01:10:27 PM PDT 24
Peak memory 203664 kb
Host smart-9fb98e96-7ed5-4f2a-93ce-5a0df6749075
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1262916940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.1262916940
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.2072089054
Short name T182
Test name
Test status
Simulation time 8958303713 ps
CPU time 9.24 seconds
Started Mar 10 01:10:25 PM PDT 24
Finished Mar 10 01:10:34 PM PDT 24
Peak memory 203732 kb
Host smart-f8f32f17-1507-4c5b-9fb4-c6fc000b5d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072089054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2072089054
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.835666069
Short name T193
Test name
Test status
Simulation time 104710011 ps
CPU time 0.67 seconds
Started Mar 10 01:10:24 PM PDT 24
Finished Mar 10 01:10:24 PM PDT 24
Peak memory 203368 kb
Host smart-2286a2d7-752f-4b09-bec7-68b9d626a140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835666069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.835666069
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.4269795310
Short name T198
Test name
Test status
Simulation time 10258782396 ps
CPU time 10.31 seconds
Started Mar 10 01:10:25 PM PDT 24
Finished Mar 10 01:10:36 PM PDT 24
Peak memory 203712 kb
Host smart-83d6c48c-75b0-4e9d-869c-b00eadf79779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269795310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.4269795310
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.1136717743
Short name T36
Test name
Test status
Simulation time 1933042037 ps
CPU time 6.6 seconds
Started Mar 10 01:10:23 PM PDT 24
Finished Mar 10 01:10:30 PM PDT 24
Peak memory 203700 kb
Host smart-5ee90e79-ad14-4c66-ac49-ff7e8f69db9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136717743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1136717743
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.4103530371
Short name T123
Test name
Test status
Simulation time 26253664 ps
CPU time 0.7 seconds
Started Mar 10 01:10:32 PM PDT 24
Finished Mar 10 01:10:33 PM PDT 24
Peak memory 203364 kb
Host smart-a3ac559e-d167-40c0-895e-ce47f1fafde2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103530371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.4103530371
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.2333507749
Short name T178
Test name
Test status
Simulation time 1660846224 ps
CPU time 6.12 seconds
Started Mar 10 01:10:25 PM PDT 24
Finished Mar 10 01:10:32 PM PDT 24
Peak memory 203628 kb
Host smart-86126cab-fec3-405e-b824-6bd8c0c1ff70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333507749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2333507749
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.813782280
Short name T189
Test name
Test status
Simulation time 6662971642 ps
CPU time 25.07 seconds
Started Mar 10 01:10:25 PM PDT 24
Finished Mar 10 01:10:50 PM PDT 24
Peak memory 203600 kb
Host smart-d276cc9d-e5dc-4515-b740-38b0af38572d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=813782280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t
l_access.813782280
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.2724284503
Short name T206
Test name
Test status
Simulation time 5846589613 ps
CPU time 19.45 seconds
Started Mar 10 01:10:25 PM PDT 24
Finished Mar 10 01:10:44 PM PDT 24
Peak memory 203712 kb
Host smart-3f05598f-a296-4a66-ad0a-a5c373bd13d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724284503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.2724284503
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.4170201290
Short name T145
Test name
Test status
Simulation time 30993789 ps
CPU time 0.66 seconds
Started Mar 10 01:10:28 PM PDT 24
Finished Mar 10 01:10:29 PM PDT 24
Peak memory 203328 kb
Host smart-b6297d64-d1f1-4641-ace4-fa0ad545ec7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170201290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.4170201290
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1119189944
Short name T180
Test name
Test status
Simulation time 1039721088 ps
CPU time 2.84 seconds
Started Mar 10 01:10:30 PM PDT 24
Finished Mar 10 01:10:33 PM PDT 24
Peak memory 203680 kb
Host smart-73df04e1-6799-4252-8b00-b0b01962b21e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1119189944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.1119189944
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1520265532
Short name T227
Test name
Test status
Simulation time 1635446649 ps
CPU time 2.07 seconds
Started Mar 10 01:10:37 PM PDT 24
Finished Mar 10 01:10:39 PM PDT 24
Peak memory 203708 kb
Host smart-68732068-6cb4-474f-b260-64391dd5624d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520265532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1520265532
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1631219970
Short name T60
Test name
Test status
Simulation time 34590519 ps
CPU time 0.65 seconds
Started Mar 10 01:10:35 PM PDT 24
Finished Mar 10 01:10:36 PM PDT 24
Peak memory 203380 kb
Host smart-0b5a31e7-9493-487c-b86a-e78d9acad61e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631219970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1631219970
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.3282034087
Short name T61
Test name
Test status
Simulation time 3069180214 ps
CPU time 13.18 seconds
Started Mar 10 01:10:28 PM PDT 24
Finished Mar 10 01:10:41 PM PDT 24
Peak memory 203732 kb
Host smart-a103473d-450d-47de-aa37-bd0c7d8d2865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282034087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3282034087
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1085071993
Short name T191
Test name
Test status
Simulation time 10814284490 ps
CPU time 7.97 seconds
Started Mar 10 01:10:28 PM PDT 24
Finished Mar 10 01:10:36 PM PDT 24
Peak memory 203772 kb
Host smart-6faabb5c-1271-40c3-ae47-ceb5bc34817c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1085071993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.1085071993
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.1359014599
Short name T171
Test name
Test status
Simulation time 2117048644 ps
CPU time 4.74 seconds
Started Mar 10 01:10:25 PM PDT 24
Finished Mar 10 01:10:30 PM PDT 24
Peak memory 203632 kb
Host smart-a80290d0-425f-440b-9d65-cad7936b9a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359014599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1359014599
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.1906064159
Short name T142
Test name
Test status
Simulation time 49794906 ps
CPU time 0.67 seconds
Started Mar 10 01:10:06 PM PDT 24
Finished Mar 10 01:10:07 PM PDT 24
Peak memory 203428 kb
Host smart-3c423b2e-ef41-463a-b4af-5a3b2048136d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906064159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1906064159
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.1491470208
Short name T76
Test name
Test status
Simulation time 34707958966 ps
CPU time 102.02 seconds
Started Mar 10 01:10:07 PM PDT 24
Finished Mar 10 01:11:49 PM PDT 24
Peak memory 211936 kb
Host smart-edfaa63b-12e4-4915-8e3f-4df3a1378675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491470208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.1491470208
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3326975277
Short name T77
Test name
Test status
Simulation time 6420797259 ps
CPU time 14.41 seconds
Started Mar 10 01:10:06 PM PDT 24
Finished Mar 10 01:10:20 PM PDT 24
Peak memory 203736 kb
Host smart-8683809d-a0f9-4ef2-8e50-6dca7e0cd85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326975277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3326975277
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.289143041
Short name T192
Test name
Test status
Simulation time 7436729294 ps
CPU time 28.22 seconds
Started Mar 10 01:10:04 PM PDT 24
Finished Mar 10 01:10:33 PM PDT 24
Peak memory 203480 kb
Host smart-7d8ae1fe-c9b2-4023-b1da-41d1a2866592
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=289143041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl
_access.289143041
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1204409988
Short name T183
Test name
Test status
Simulation time 179201259 ps
CPU time 0.74 seconds
Started Mar 10 01:10:03 PM PDT 24
Finished Mar 10 01:10:04 PM PDT 24
Peak memory 203020 kb
Host smart-f4652710-86c1-44a7-99e0-d2471862f25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204409988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1204409988
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1357899135
Short name T44
Test name
Test status
Simulation time 107411027 ps
CPU time 1.22 seconds
Started Mar 10 01:10:04 PM PDT 24
Finished Mar 10 01:10:06 PM PDT 24
Peak memory 219580 kb
Host smart-0a6652d5-52c4-4194-b36d-76e1a9b7c4c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357899135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1357899135
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2921545110
Short name T156
Test name
Test status
Simulation time 155948861 ps
CPU time 0.7 seconds
Started Mar 10 01:10:27 PM PDT 24
Finished Mar 10 01:10:28 PM PDT 24
Peak memory 203364 kb
Host smart-b29fb621-3ec0-471e-b443-c5176728eb08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921545110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2921545110
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1164450954
Short name T148
Test name
Test status
Simulation time 113164009 ps
CPU time 0.64 seconds
Started Mar 10 01:10:31 PM PDT 24
Finished Mar 10 01:10:32 PM PDT 24
Peak memory 203364 kb
Host smart-c6fb3318-f9e5-459b-9076-620b9fa5c28b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164450954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1164450954
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.792137784
Short name T164
Test name
Test status
Simulation time 30561067 ps
CPU time 0.7 seconds
Started Mar 10 01:10:27 PM PDT 24
Finished Mar 10 01:10:27 PM PDT 24
Peak memory 203440 kb
Host smart-059dbb4e-5e14-4551-b1a9-fab4e7af13dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792137784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.792137784
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.1158328280
Short name T228
Test name
Test status
Simulation time 18163169 ps
CPU time 0.64 seconds
Started Mar 10 01:10:34 PM PDT 24
Finished Mar 10 01:10:35 PM PDT 24
Peak memory 203380 kb
Host smart-9894f6ce-70d5-432d-8d4f-74085524b35e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158328280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1158328280
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.51620540
Short name T188
Test name
Test status
Simulation time 25065901 ps
CPU time 0.7 seconds
Started Mar 10 01:10:32 PM PDT 24
Finished Mar 10 01:10:33 PM PDT 24
Peak memory 203324 kb
Host smart-b435febc-2bb8-434c-ad87-dd1dd39f4e72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51620540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.51620540
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3731376257
Short name T43
Test name
Test status
Simulation time 58626147 ps
CPU time 0.63 seconds
Started Mar 10 01:10:37 PM PDT 24
Finished Mar 10 01:10:37 PM PDT 24
Peak memory 203392 kb
Host smart-baca1bd2-260f-4cd2-ba43-5b54380e2a55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731376257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3731376257
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.3215730654
Short name T159
Test name
Test status
Simulation time 49892849 ps
CPU time 0.63 seconds
Started Mar 10 01:10:31 PM PDT 24
Finished Mar 10 01:10:32 PM PDT 24
Peak memory 203360 kb
Host smart-1b9333f3-5ed5-4990-9f96-2d73ad9d1141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215730654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3215730654
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.2787748697
Short name T140
Test name
Test status
Simulation time 71157454 ps
CPU time 0.65 seconds
Started Mar 10 01:10:34 PM PDT 24
Finished Mar 10 01:10:34 PM PDT 24
Peak memory 203332 kb
Host smart-e218cda2-8de1-4af2-8113-364df5779548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787748697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.2787748697
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.848253229
Short name T152
Test name
Test status
Simulation time 41738781 ps
CPU time 0.67 seconds
Started Mar 10 01:10:33 PM PDT 24
Finished Mar 10 01:10:33 PM PDT 24
Peak memory 203384 kb
Host smart-fe6fbc33-4e82-42e9-93d8-c0eb6c01f53a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848253229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.848253229
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.1642636955
Short name T149
Test name
Test status
Simulation time 46734082 ps
CPU time 0.66 seconds
Started Mar 10 01:10:35 PM PDT 24
Finished Mar 10 01:10:35 PM PDT 24
Peak memory 203372 kb
Host smart-a35e46a4-5e8b-495b-b40c-2c1769f184f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642636955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1642636955
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.636386784
Short name T155
Test name
Test status
Simulation time 55672660 ps
CPU time 0.65 seconds
Started Mar 10 01:10:12 PM PDT 24
Finished Mar 10 01:10:13 PM PDT 24
Peak memory 203428 kb
Host smart-8203a349-c7d0-4917-aa8a-b137305371f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636386784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.636386784
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.2662092444
Short name T63
Test name
Test status
Simulation time 11119719719 ps
CPU time 18.74 seconds
Started Mar 10 01:10:05 PM PDT 24
Finished Mar 10 01:10:24 PM PDT 24
Peak memory 203728 kb
Host smart-3788b4b4-7e1a-4084-9fed-e036edb01e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662092444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2662092444
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.2179015706
Short name T212
Test name
Test status
Simulation time 8049607300 ps
CPU time 9.54 seconds
Started Mar 10 01:10:04 PM PDT 24
Finished Mar 10 01:10:14 PM PDT 24
Peak memory 203744 kb
Host smart-b58fca8d-adb0-4f78-b219-57110a25bb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179015706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2179015706
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.957840299
Short name T194
Test name
Test status
Simulation time 89814284 ps
CPU time 0.8 seconds
Started Mar 10 01:10:03 PM PDT 24
Finished Mar 10 01:10:04 PM PDT 24
Peak memory 202976 kb
Host smart-2bc23420-ec3e-417d-94bb-f29b979779a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957840299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.957840299
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1983897968
Short name T190
Test name
Test status
Simulation time 6245356020 ps
CPU time 7.29 seconds
Started Mar 10 01:10:05 PM PDT 24
Finished Mar 10 01:10:13 PM PDT 24
Peak memory 203704 kb
Host smart-8024e696-8744-4526-93cf-79ffb9c0dee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983897968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1983897968
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.905546087
Short name T45
Test name
Test status
Simulation time 160306445 ps
CPU time 1.24 seconds
Started Mar 10 01:10:11 PM PDT 24
Finished Mar 10 01:10:13 PM PDT 24
Peak memory 219736 kb
Host smart-761591af-4280-4c68-b050-83b1af4d85ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905546087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.905546087
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3465609704
Short name T172
Test name
Test status
Simulation time 28543925 ps
CPU time 0.67 seconds
Started Mar 10 01:10:36 PM PDT 24
Finished Mar 10 01:10:36 PM PDT 24
Peak memory 203356 kb
Host smart-3369b2bf-7237-45e2-b1ea-75ac41bba96e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465609704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3465609704
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.70984082
Short name T184
Test name
Test status
Simulation time 57028864 ps
CPU time 0.67 seconds
Started Mar 10 01:10:38 PM PDT 24
Finished Mar 10 01:10:39 PM PDT 24
Peak memory 203440 kb
Host smart-df927278-cfbb-478a-8f55-6405b4d82115
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70984082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.70984082
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.941034892
Short name T147
Test name
Test status
Simulation time 29478265 ps
CPU time 0.73 seconds
Started Mar 10 01:10:40 PM PDT 24
Finished Mar 10 01:10:41 PM PDT 24
Peak memory 203260 kb
Host smart-25c48d13-a2d1-4826-9195-a329af9f35c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941034892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.941034892
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.3952490203
Short name T144
Test name
Test status
Simulation time 50386657 ps
CPU time 0.68 seconds
Started Mar 10 01:10:38 PM PDT 24
Finished Mar 10 01:10:38 PM PDT 24
Peak memory 203408 kb
Host smart-a5c5e8a1-a7f9-4b04-a12f-2e51f2e5c9ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952490203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3952490203
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.2020917734
Short name T41
Test name
Test status
Simulation time 1625998303 ps
CPU time 5.78 seconds
Started Mar 10 01:10:40 PM PDT 24
Finished Mar 10 01:10:46 PM PDT 24
Peak memory 203500 kb
Host smart-6d1a6af0-0ff2-4fe6-a269-0eed0d51bf1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020917734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2020917734
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.2919537042
Short name T39
Test name
Test status
Simulation time 70461754 ps
CPU time 0.66 seconds
Started Mar 10 01:10:40 PM PDT 24
Finished Mar 10 01:10:41 PM PDT 24
Peak memory 203260 kb
Host smart-59e3d2b5-9cac-4704-9b49-6925b4b15a99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919537042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2919537042
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.2916787982
Short name T201
Test name
Test status
Simulation time 23979099 ps
CPU time 0.7 seconds
Started Mar 10 01:10:40 PM PDT 24
Finished Mar 10 01:10:41 PM PDT 24
Peak memory 203384 kb
Host smart-6abaf369-6080-4922-99ae-36fd50446fd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916787982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2916787982
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.90653952
Short name T42
Test name
Test status
Simulation time 19160057 ps
CPU time 0.7 seconds
Started Mar 10 01:10:46 PM PDT 24
Finished Mar 10 01:10:47 PM PDT 24
Peak memory 203344 kb
Host smart-e669127d-4398-473f-8deb-89257fa1206f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90653952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.90653952
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.908017303
Short name T86
Test name
Test status
Simulation time 19090412 ps
CPU time 0.67 seconds
Started Mar 10 01:10:38 PM PDT 24
Finished Mar 10 01:10:39 PM PDT 24
Peak memory 203440 kb
Host smart-a028787e-a57d-49b6-89c4-7fe4ab87d628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908017303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.908017303
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.295531518
Short name T157
Test name
Test status
Simulation time 35952378 ps
CPU time 0.69 seconds
Started Mar 10 01:10:44 PM PDT 24
Finished Mar 10 01:10:45 PM PDT 24
Peak memory 203340 kb
Host smart-af074800-a7c0-4a8e-869d-38fbc6099e85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295531518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.295531518
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3847754658
Short name T154
Test name
Test status
Simulation time 56156126 ps
CPU time 0.67 seconds
Started Mar 10 01:10:10 PM PDT 24
Finished Mar 10 01:10:12 PM PDT 24
Peak memory 203432 kb
Host smart-9c1c3efd-bc34-4557-8bb5-d1feb093f47c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847754658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3847754658
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1592654155
Short name T214
Test name
Test status
Simulation time 12772914560 ps
CPU time 17.52 seconds
Started Mar 10 01:10:11 PM PDT 24
Finished Mar 10 01:10:29 PM PDT 24
Peak memory 203736 kb
Host smart-44ee7649-0d78-420b-8df0-0e7f1ab9efcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592654155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1592654155
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1862503864
Short name T165
Test name
Test status
Simulation time 4105957191 ps
CPU time 14.34 seconds
Started Mar 10 01:10:09 PM PDT 24
Finished Mar 10 01:10:23 PM PDT 24
Peak memory 203696 kb
Host smart-7a563e87-ab2c-43a1-b871-3a5bb9ef04f9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1862503864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.1862503864
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.3204416173
Short name T169
Test name
Test status
Simulation time 90496475 ps
CPU time 0.75 seconds
Started Mar 10 01:10:10 PM PDT 24
Finished Mar 10 01:10:11 PM PDT 24
Peak memory 203344 kb
Host smart-4a87aaf1-bc56-4401-8622-073ee7714168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204416173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3204416173
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.21308485
Short name T208
Test name
Test status
Simulation time 5805973279 ps
CPU time 8.85 seconds
Started Mar 10 01:10:10 PM PDT 24
Finished Mar 10 01:10:20 PM PDT 24
Peak memory 203740 kb
Host smart-24e17dd1-9839-45b9-9a71-0c2a080bdb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21308485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.21308485
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.2187839992
Short name T75
Test name
Test status
Simulation time 158230618 ps
CPU time 1.33 seconds
Started Mar 10 01:10:10 PM PDT 24
Finished Mar 10 01:10:12 PM PDT 24
Peak memory 219384 kb
Host smart-0f6ac2a6-2bee-4e98-a5b8-715d6f4360d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187839992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2187839992
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.1719429023
Short name T87
Test name
Test status
Simulation time 4149355762 ps
CPU time 13.14 seconds
Started Mar 10 01:10:11 PM PDT 24
Finished Mar 10 01:10:25 PM PDT 24
Peak memory 203536 kb
Host smart-64c41041-816e-40e8-a52d-858673d9ff5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719429023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.1719429023
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.753346746
Short name T231
Test name
Test status
Simulation time 51520522 ps
CPU time 0.66 seconds
Started Mar 10 01:10:41 PM PDT 24
Finished Mar 10 01:10:42 PM PDT 24
Peak memory 203396 kb
Host smart-17c5e456-906d-492d-a7cb-d6d9ca581199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753346746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.753346746
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.33687828
Short name T209
Test name
Test status
Simulation time 20156368 ps
CPU time 0.68 seconds
Started Mar 10 01:10:38 PM PDT 24
Finished Mar 10 01:10:38 PM PDT 24
Peak memory 203432 kb
Host smart-6b2e62ca-6795-4476-b756-e14e0d0306da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33687828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.33687828
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.4042450977
Short name T25
Test name
Test status
Simulation time 2018266361 ps
CPU time 6.15 seconds
Started Mar 10 01:10:40 PM PDT 24
Finished Mar 10 01:10:47 PM PDT 24
Peak memory 203524 kb
Host smart-c420f2b0-46db-4608-b18e-00a16b0d7c28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042450977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.4042450977
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.975723601
Short name T59
Test name
Test status
Simulation time 59517296 ps
CPU time 0.69 seconds
Started Mar 10 01:10:46 PM PDT 24
Finished Mar 10 01:10:47 PM PDT 24
Peak memory 203344 kb
Host smart-95526124-ec15-4eff-90a7-f32b995e0501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975723601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.975723601
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.27723150
Short name T71
Test name
Test status
Simulation time 5223054830 ps
CPU time 2.9 seconds
Started Mar 10 01:10:40 PM PDT 24
Finished Mar 10 01:10:43 PM PDT 24
Peak memory 203572 kb
Host smart-d0682f1c-638a-4485-b411-48f671f34718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27723150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.27723150
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.325948491
Short name T151
Test name
Test status
Simulation time 67544900 ps
CPU time 0.65 seconds
Started Mar 10 01:10:45 PM PDT 24
Finished Mar 10 01:10:46 PM PDT 24
Peak memory 203464 kb
Host smart-72f22585-9d10-45e2-ba7c-3cd5d20c4f6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325948491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.325948491
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.869036863
Short name T177
Test name
Test status
Simulation time 32259269 ps
CPU time 0.68 seconds
Started Mar 10 01:10:43 PM PDT 24
Finished Mar 10 01:10:44 PM PDT 24
Peak memory 203324 kb
Host smart-1713f0dd-81a0-472d-ae85-726ad3b3d274
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869036863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.869036863
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.263569743
Short name T233
Test name
Test status
Simulation time 28464552 ps
CPU time 0.65 seconds
Started Mar 10 01:10:42 PM PDT 24
Finished Mar 10 01:10:43 PM PDT 24
Peak memory 203336 kb
Host smart-d569b775-97d7-4a82-8586-1a78a63caa19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263569743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.263569743
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.2222711939
Short name T211
Test name
Test status
Simulation time 27405579 ps
CPU time 0.68 seconds
Started Mar 10 01:10:45 PM PDT 24
Finished Mar 10 01:10:45 PM PDT 24
Peak memory 203368 kb
Host smart-a8ffcdf6-bcd1-4ac3-86e3-df3634193831
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222711939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2222711939
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.1578538397
Short name T33
Test name
Test status
Simulation time 3797179275 ps
CPU time 8.35 seconds
Started Mar 10 01:10:45 PM PDT 24
Finished Mar 10 01:10:53 PM PDT 24
Peak memory 203596 kb
Host smart-bf198b22-fec3-41ba-acb8-2bf048d9e36e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578538397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.1578538397
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2006939289
Short name T163
Test name
Test status
Simulation time 19427419 ps
CPU time 0.68 seconds
Started Mar 10 01:10:44 PM PDT 24
Finished Mar 10 01:10:45 PM PDT 24
Peak memory 203420 kb
Host smart-20d049e8-f84c-4707-8c58-a7894cad1138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006939289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2006939289
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.179445507
Short name T58
Test name
Test status
Simulation time 68324995 ps
CPU time 0.65 seconds
Started Mar 10 01:10:44 PM PDT 24
Finished Mar 10 01:10:44 PM PDT 24
Peak memory 203312 kb
Host smart-2bd64d9a-1f94-4ece-9f19-33d9c79db1bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179445507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.179445507
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.2024207827
Short name T141
Test name
Test status
Simulation time 97909975 ps
CPU time 0.72 seconds
Started Mar 10 01:10:50 PM PDT 24
Finished Mar 10 01:10:51 PM PDT 24
Peak memory 203436 kb
Host smart-96881c2c-459e-4c07-bd25-d79e2eae3e0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024207827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2024207827
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2919577797
Short name T181
Test name
Test status
Simulation time 36877164 ps
CPU time 0.66 seconds
Started Mar 10 01:10:08 PM PDT 24
Finished Mar 10 01:10:09 PM PDT 24
Peak memory 203208 kb
Host smart-2c850612-7c1b-407d-b529-bd9fd5cd5c9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919577797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2919577797
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.275321146
Short name T170
Test name
Test status
Simulation time 8613405776 ps
CPU time 40.55 seconds
Started Mar 10 01:10:09 PM PDT 24
Finished Mar 10 01:10:50 PM PDT 24
Peak memory 203752 kb
Host smart-a2e7efdb-b67b-4693-8089-2a51cbeae515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275321146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.275321146
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.1881456420
Short name T196
Test name
Test status
Simulation time 3107133399 ps
CPU time 6.89 seconds
Started Mar 10 01:10:10 PM PDT 24
Finished Mar 10 01:10:18 PM PDT 24
Peak memory 203648 kb
Host smart-411593be-5344-48ce-b42e-d2db19e2b890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881456420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1881456420
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.150058975
Short name T195
Test name
Test status
Simulation time 2058024330 ps
CPU time 4.24 seconds
Started Mar 10 01:10:12 PM PDT 24
Finished Mar 10 01:10:17 PM PDT 24
Peak memory 203684 kb
Host smart-6ffdd139-632f-477e-895e-370b11ea10ed
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=150058975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl
_access.150058975
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.1980283646
Short name T168
Test name
Test status
Simulation time 4572899108 ps
CPU time 7.45 seconds
Started Mar 10 01:10:12 PM PDT 24
Finished Mar 10 01:10:20 PM PDT 24
Peak memory 203684 kb
Host smart-97feb1a7-f676-42dd-981a-b2c464522549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980283646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1980283646
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2326528192
Short name T162
Test name
Test status
Simulation time 51517777 ps
CPU time 0.65 seconds
Started Mar 10 01:10:10 PM PDT 24
Finished Mar 10 01:10:11 PM PDT 24
Peak memory 203408 kb
Host smart-63e62c24-7160-4cc5-a38f-460001618952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326528192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2326528192
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2327650630
Short name T1
Test name
Test status
Simulation time 32319052607 ps
CPU time 50.59 seconds
Started Mar 10 01:10:14 PM PDT 24
Finished Mar 10 01:11:06 PM PDT 24
Peak memory 203792 kb
Host smart-ae86fed3-a14e-41a2-b1b9-3b7497a36f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327650630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2327650630
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.301557263
Short name T38
Test name
Test status
Simulation time 3165094923 ps
CPU time 11.27 seconds
Started Mar 10 01:10:11 PM PDT 24
Finished Mar 10 01:10:23 PM PDT 24
Peak memory 203776 kb
Host smart-89ed8292-e405-49cc-a182-27e0001374aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301557263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.301557263
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3892637802
Short name T224
Test name
Test status
Simulation time 2947710559 ps
CPU time 2.84 seconds
Started Mar 10 01:10:17 PM PDT 24
Finished Mar 10 01:10:22 PM PDT 24
Peak memory 203788 kb
Host smart-a349aabb-1a2c-4fec-aa1e-0fb00c69ac72
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3892637802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.3892637802
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.1529179640
Short name T232
Test name
Test status
Simulation time 4435254610 ps
CPU time 8.07 seconds
Started Mar 10 01:10:09 PM PDT 24
Finished Mar 10 01:10:18 PM PDT 24
Peak memory 203676 kb
Host smart-9a84e305-9c7d-4ab9-a5b6-f4b605dcf7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529179640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1529179640
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2160128529
Short name T153
Test name
Test status
Simulation time 56046994 ps
CPU time 0.7 seconds
Started Mar 10 01:10:10 PM PDT 24
Finished Mar 10 01:10:12 PM PDT 24
Peak memory 203360 kb
Host smart-6dae0aee-382f-4977-b8b8-a4c2a84c7254
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160128529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2160128529
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.286857290
Short name T187
Test name
Test status
Simulation time 1737802055 ps
CPU time 6.51 seconds
Started Mar 10 01:10:12 PM PDT 24
Finished Mar 10 01:10:20 PM PDT 24
Peak memory 203628 kb
Host smart-5ef211c0-4faf-4972-9743-1e546026307e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286857290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.286857290
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2987627497
Short name T225
Test name
Test status
Simulation time 2399502887 ps
CPU time 7.47 seconds
Started Mar 10 01:10:17 PM PDT 24
Finished Mar 10 01:10:26 PM PDT 24
Peak memory 203676 kb
Host smart-6a73cf45-f6f4-4150-9bd1-fbe2fd94a0b2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2987627497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.2987627497
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.1133183607
Short name T221
Test name
Test status
Simulation time 3487766726 ps
CPU time 12.91 seconds
Started Mar 10 01:10:11 PM PDT 24
Finished Mar 10 01:10:25 PM PDT 24
Peak memory 203764 kb
Host smart-dc81c8a2-d775-4fd0-a8cd-cc422a961f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133183607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1133183607
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.406485439
Short name T57
Test name
Test status
Simulation time 53902874 ps
CPU time 0.63 seconds
Started Mar 10 01:10:16 PM PDT 24
Finished Mar 10 01:10:17 PM PDT 24
Peak memory 203336 kb
Host smart-ac5974f3-1c68-4679-a5e8-c227eaed0580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406485439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.406485439
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.931353919
Short name T217
Test name
Test status
Simulation time 2339160589 ps
CPU time 10.53 seconds
Started Mar 10 01:10:09 PM PDT 24
Finished Mar 10 01:10:21 PM PDT 24
Peak memory 203596 kb
Host smart-ed1b9fb0-7faa-4a6e-bef9-a46e8778695f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931353919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.931353919
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1164672936
Short name T226
Test name
Test status
Simulation time 3570726588 ps
CPU time 5.43 seconds
Started Mar 10 01:10:12 PM PDT 24
Finished Mar 10 01:10:18 PM PDT 24
Peak memory 203772 kb
Host smart-3e0727a0-cd37-46e5-ae1e-c84882811749
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1164672936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.1164672936
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.985997915
Short name T215
Test name
Test status
Simulation time 550458918 ps
CPU time 2.73 seconds
Started Mar 10 01:10:12 PM PDT 24
Finished Mar 10 01:10:15 PM PDT 24
Peak memory 203720 kb
Host smart-ce620a49-7fe6-400e-ab9d-a612c307fe0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985997915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.985997915
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1006138132
Short name T54
Test name
Test status
Simulation time 45891705 ps
CPU time 0.69 seconds
Started Mar 10 01:10:15 PM PDT 24
Finished Mar 10 01:10:17 PM PDT 24
Peak memory 203388 kb
Host smart-d877a008-80c5-44f0-8da8-2892e6dc831e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006138132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1006138132
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.3966624725
Short name T222
Test name
Test status
Simulation time 2847284407 ps
CPU time 5.96 seconds
Started Mar 10 01:10:18 PM PDT 24
Finished Mar 10 01:10:25 PM PDT 24
Peak memory 203720 kb
Host smart-64203d71-3ef6-4063-a139-350a1bf2b2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966624725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3966624725
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2213368839
Short name T166
Test name
Test status
Simulation time 928001391 ps
CPU time 5.49 seconds
Started Mar 10 01:10:14 PM PDT 24
Finished Mar 10 01:10:21 PM PDT 24
Peak memory 203648 kb
Host smart-be344d4b-5e1e-45e4-9a67-6529f77fd337
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2213368839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.2213368839
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1399656543
Short name T175
Test name
Test status
Simulation time 791783391 ps
CPU time 2.03 seconds
Started Mar 10 01:10:15 PM PDT 24
Finished Mar 10 01:10:18 PM PDT 24
Peak memory 203700 kb
Host smart-4b4fb0a8-8c53-4d9d-9046-c749bb73d531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399656543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1399656543
Directory /workspace/9.rv_dm_sba_tl_access/latest
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