Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	224102	1		T7	6		T4	80		T8	3
full_word	526732	1		T7	1		T16	2		T4	29

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	750574	1		T7	7		T16	2		T4	109
auto[TlIntgErrCmd]	86	1		T42	3		T43	8		T44	4
auto[TlIntgErrData]	83	1		T42	4		T43	5		T44	5
auto[TlIntgErrBoth]	91	1		T42	3		T43	7		T44	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	462105	1		T4	24		T5	4		T17	20
auto[1]	288729	1		T7	7		T16	2		T4	85

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	185746	1		T4	15		T5	1		T17	9
auto[TlIntgErrNone]	partial	auto[1]	38116	1		T7	6		T4	65		T8	3
auto[TlIntgErrNone]	full_word	auto[0]	276230	1		T4	9		T5	3		T17	11
auto[TlIntgErrNone]	full_word	auto[1]	250482	1		T7	1		T16	2		T4	20
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T43	3		T44	4		T80	1
auto[TlIntgErrCmd]	partial	auto[1]	40	1		T42	3		T43	4		T79	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T77	1		T123	1		T117	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T43	1		T79	1		T124	2
auto[TlIntgErrData]	partial	auto[0]	51	1		T42	2		T43	3		T44	3
auto[TlIntgErrData]	partial	auto[1]	29	1		T42	2		T43	2		T44	1
auto[TlIntgErrData]	full_word	auto[0]	2	1		T44	1		T80	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	1	1		T120	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	34	1		T42	2		T43	2		T44	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1		T42	1		T43	5		T79	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T125	2		T119	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T77	1		T120	1		T126	1