Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	192023	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	525397	1		T7	1		T16	2		T4	29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	460478	1		T4	24		T5	4		T17	20
values[0x0]	126400	1		T7	4		T16	2		T4	39
values[0x1]	130542	1		T7	3		T4	46		T8	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	146862	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	570558	1		T7	1		T16	2		T4	37

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3168	1		T35	1		T48	28		T69	3
valid_sources[0x01]	3611	1		T48	28		T69	2		T50	6
valid_sources[0x02]	3348	1		T18	1		T28	1		T48	33
valid_sources[0x03]	2230	1		T48	22		T69	1		T49	5
valid_sources[0x04]	2576	1		T18	2		T29	1		T48	30
valid_sources[0x05]	3273	1		T48	36		T69	1		T50	5
valid_sources[0x06]	3486	1		T35	1		T48	14		T69	1
valid_sources[0x07]	2299	1		T18	1		T29	1		T48	26
valid_sources[0x08]	2622	1		T4	3		T18	1		T48	18
valid_sources[0x09]	3384	1		T18	1		T35	1		T48	29
valid_sources[0x0a]	3065	1		T4	1		T29	1		T48	14
valid_sources[0x0b]	2500	1		T35	1		T128	1		T48	24
valid_sources[0x0c]	2664	1		T28	2		T48	27		T69	2
valid_sources[0x0d]	3688	1		T128	1		T48	26		T69	4
valid_sources[0x0e]	2690	1		T18	1		T116	1		T31	25
valid_sources[0x0f]	3670	1		T24	1		T18	2		T28	1
valid_sources[0x10]	2624	1		T12	6		T48	22		T69	1
valid_sources[0x11]	2808	1		T5	9		T28	1		T29	1
valid_sources[0x12]	2879	1		T128	1		T48	22		T69	1
valid_sources[0x13]	2287	1		T128	1		T48	21		T69	1
valid_sources[0x14]	2697	1		T5	1		T17	5		T35	2
valid_sources[0x15]	3281	1		T28	2		T34	6		T29	1
valid_sources[0x16]	2751	1		T35	1		T48	19		T69	2
valid_sources[0x17]	2588	1		T18	2		T31	2		T35	1
valid_sources[0x18]	3138	1		T4	2		T28	1		T35	1
valid_sources[0x19]	2635	1		T4	1		T24	2		T18	2
valid_sources[0x1a]	2498	1		T18	1		T29	1		T48	18
valid_sources[0x1b]	3143	1		T17	7		T18	4		T48	33
valid_sources[0x1c]	2555	1		T5	4		T24	1		T34	1
valid_sources[0x1d]	3102	1		T4	1		T34	1		T48	22
valid_sources[0x1e]	2460	1		T35	2		T29	1		T48	23
valid_sources[0x1f]	3687	1		T35	2		T48	18		T49	1
valid_sources[0x20]	3751	1		T48	32		T69	1		T55	1
valid_sources[0x21]	2462	1		T18	2		T34	2		T35	1
valid_sources[0x22]	2837	1		T48	25		T69	3		T49	14
valid_sources[0x23]	3079	1		T48	25		T69	2		T49	2
valid_sources[0x24]	2557	1		T35	1		T48	27		T69	3
valid_sources[0x25]	2312	1		T5	1		T48	18		T69	2
valid_sources[0x26]	2564	1		T116	1		T29	1		T48	36
valid_sources[0x27]	2650	1		T48	27		T49	13		T50	6
valid_sources[0x28]	3467	1		T129	2		T128	2		T48	20
valid_sources[0x29]	3058	1		T4	3		T35	1		T48	20
valid_sources[0x2a]	2390	1		T48	22		T69	4		T49	4
valid_sources[0x2b]	2827	1		T34	4		T35	1		T29	1
valid_sources[0x2c]	3196	1		T4	6		T35	3		T48	15
valid_sources[0x2d]	3625	1		T28	2		T34	4		T35	1
valid_sources[0x2e]	2269	1		T18	1		T35	1		T48	27
valid_sources[0x2f]	2589	1		T5	2		T18	1		T35	2
valid_sources[0x30]	2758	1		T35	1		T48	26		T49	4
valid_sources[0x31]	2906	1		T17	8		T18	1		T29	1
valid_sources[0x32]	2343	1		T28	1		T48	22		T69	1
valid_sources[0x33]	2738	1		T116	2		T48	25		T69	4
valid_sources[0x34]	2669	1		T17	6		T28	1		T48	22
valid_sources[0x35]	2521	1		T4	3		T34	6		T48	16
valid_sources[0x36]	2025	1		T4	3		T28	1		T34	4
valid_sources[0x37]	2898	1		T4	1		T5	3		T48	21
valid_sources[0x38]	2906	1		T48	19		T69	3		T50	3
valid_sources[0x39]	2516	1		T48	18		T69	1		T49	1
valid_sources[0x3a]	2606	1		T48	17		T49	6		T50	4
valid_sources[0x3b]	2745	1		T7	1		T28	1		T48	26
valid_sources[0x3c]	2651	1		T116	2		T32	1		T35	2
valid_sources[0x3d]	2902	1		T24	2		T28	2		T29	1
valid_sources[0x3e]	2703	1		T18	2		T48	26		T69	2
valid_sources[0x3f]	2658	1		T28	1		T128	1		T48	25
valid_sources[0x40]	3477	1		T35	4		T29	1		T48	16
valid_sources[0x41]	2799	1		T17	5		T18	1		T35	1
valid_sources[0x42]	2334	1		T18	8		T48	18		T69	3
valid_sources[0x43]	2864	1		T28	1		T35	2		T48	21
valid_sources[0x44]	3128	1		T24	2		T18	3		T29	2
valid_sources[0x45]	2649	1		T17	3		T28	1		T35	3
valid_sources[0x46]	3043	1		T34	3		T48	18		T69	3
valid_sources[0x47]	2558	1		T5	2		T34	2		T35	1
valid_sources[0x48]	2807	1		T4	4		T28	2		T48	34
valid_sources[0x49]	3005	1		T4	1		T48	28		T69	1
valid_sources[0x4a]	2652	1		T18	1		T34	2		T48	21
valid_sources[0x4b]	2395	1		T35	1		T128	1		T48	26
valid_sources[0x4c]	3383	1		T18	4		T35	2		T48	23
valid_sources[0x4d]	2932	1		T6	1		T48	17		T69	2
valid_sources[0x4e]	2758	1		T29	1		T48	29		T49	3
valid_sources[0x4f]	2543	1		T18	2		T28	2		T29	2
valid_sources[0x50]	2446	1		T34	1		T35	1		T48	23
valid_sources[0x51]	3030	1		T7	1		T18	1		T35	1
valid_sources[0x52]	2016	1		T4	2		T81	16		T48	24
valid_sources[0x53]	2442	1		T18	1		T35	3		T29	1
valid_sources[0x54]	2652	1		T128	1		T48	28		T69	2
valid_sources[0x55]	2440	1		T8	1		T5	1		T48	28
valid_sources[0x56]	2694	1		T18	1		T48	19		T69	3
valid_sources[0x57]	2122	1		T48	23		T49	10		T50	7
valid_sources[0x58]	3483	1		T5	4		T18	1		T34	4
valid_sources[0x59]	1924	1		T4	1		T18	1		T48	18
valid_sources[0x5a]	2317	1		T48	25		T69	1		T49	2
valid_sources[0x5b]	2866	1		T29	1		T48	17		T69	1
valid_sources[0x5c]	3216	1		T35	2		T48	32		T69	1
valid_sources[0x5d]	2940	1		T7	1		T35	1		T48	22
valid_sources[0x5e]	3131	1		T28	1		T34	4		T48	28
valid_sources[0x5f]	2381	1		T4	4		T28	1		T48	27
valid_sources[0x60]	2674	1		T48	16		T69	4		T49	6
valid_sources[0x61]	2890	1		T28	1		T48	25		T49	8
valid_sources[0x62]	2877	1		T7	1		T34	3		T48	32
valid_sources[0x63]	2856	1		T28	1		T29	1		T48	30
valid_sources[0x64]	3012	1		T28	1		T48	18		T69	2
valid_sources[0x65]	2517	1		T28	1		T48	30		T69	2
valid_sources[0x66]	3177	1		T4	2		T18	2		T35	1
valid_sources[0x67]	2825	1		T4	4		T48	25		T69	2
valid_sources[0x68]	2842	1		T24	2		T28	1		T29	1
valid_sources[0x69]	3826	1		T28	1		T116	1		T29	1
valid_sources[0x6a]	3643	1		T4	1		T48	23		T69	1
valid_sources[0x6b]	2655	1		T35	1		T48	22		T50	10
valid_sources[0x6c]	2567	1		T28	1		T48	21		T69	4
valid_sources[0x6d]	2241	1		T29	4		T128	3		T48	14
valid_sources[0x6e]	2263	1		T128	1		T48	22		T69	4
valid_sources[0x6f]	3256	1		T28	1		T128	2		T48	23
valid_sources[0x70]	2640	1		T48	30		T49	9		T50	15
valid_sources[0x71]	3347	1		T4	2		T23	34		T28	1
valid_sources[0x72]	2400	1		T4	3		T35	1		T29	1
valid_sources[0x73]	3468	1		T4	1		T18	1		T29	1
valid_sources[0x74]	2645	1		T4	2		T48	25		T69	5
valid_sources[0x75]	2665	1		T29	1		T48	20		T69	1
valid_sources[0x76]	2599	1		T48	35		T69	2		T55	37
valid_sources[0x77]	2473	1		T28	1		T31	15		T48	24
valid_sources[0x78]	2832	1		T18	1		T34	5		T35	1
valid_sources[0x79]	2209	1		T128	2		T48	27		T69	5
valid_sources[0x7a]	2743	1		T4	1		T28	1		T48	29
valid_sources[0x7b]	3316	1		T7	1		T18	2		T128	1
valid_sources[0x7c]	2949	1		T5	5		T130	1		T48	18
valid_sources[0x7d]	3190	1		T28	1		T29	2		T48	23
valid_sources[0x7e]	3154	1		T18	2		T28	1		T35	1
valid_sources[0x7f]	2716	1		T28	1		T48	23		T69	2
valid_sources[0x80]	3417	1		T29	1		T48	20		T69	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

276039

1

T4

9

T5

3

T17

11

values[0x0]

all_enables

biggest_size

124767

1

T7

1

T16

2

T4

15

values[0x1]

all_enables

biggest_size

124591

1

T4

5

T12

5

T5

9

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2034	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	17172	1		T1	2		T2	6		T3	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5855	1		T48	1		T69	157		T49	2
values[0x0]	6560	1		T1	2		T2	4		T3	6
values[0x1]	6791	1		T1	3		T2	6		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1545	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	17661	1		T1	3		T2	7		T3	2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	58	1		T131	1		T132	1		T69	6
valid_sources[0x01]	85	1		T69	1		T50	9		T45	6
valid_sources[0x02]	57	1		T53	3		T133	2		T50	3
valid_sources[0x03]	97	1		T1	1		T134	3		T69	1
valid_sources[0x04]	38	1		T69	4		T64	2		T84	1
valid_sources[0x05]	77	1		T69	7		T50	7		T84	5
valid_sources[0x06]	58	1		T133	3		T135	1		T69	8
valid_sources[0x07]	77	1		T53	2		T136	9		T69	2
valid_sources[0x08]	99	1		T69	7		T50	3		T46	4
valid_sources[0x09]	54	1		T137	1		T69	9		T64	1
valid_sources[0x0a]	80	1		T138	1		T131	1		T50	14
valid_sources[0x0b]	47	1		T69	1		T50	6		T64	1
valid_sources[0x0c]	34	1		T139	1		T69	4		T50	3
valid_sources[0x0d]	60	1		T2	3		T140	2		T141	1
valid_sources[0x0e]	103	1		T69	4		T50	4		T64	4
valid_sources[0x0f]	46	1		T69	1		T45	2		T64	1
valid_sources[0x10]	50	1		T30	2		T69	1		T50	3
valid_sources[0x11]	63	1		T45	2		T64	4		T79	1
valid_sources[0x12]	153	1		T50	13		T45	2		T64	2
valid_sources[0x13]	79	1		T132	1		T69	1		T50	11
valid_sources[0x14]	89	1		T134	1		T142	1		T143	1
valid_sources[0x15]	33	1		T42	1		T79	1		T89	3
valid_sources[0x16]	47	1		T69	1		T45	8		T46	2
valid_sources[0x17]	48	1		T140	1		T50	1		T45	3
valid_sources[0x18]	57	1		T50	3		T64	2		T88	4
valid_sources[0x19]	122	1		T139	1		T69	3		T42	1
valid_sources[0x1a]	37	1		T144	1		T69	1		T58	2
valid_sources[0x1b]	56	1		T133	2		T69	1		T50	2
valid_sources[0x1c]	53	1		T69	3		T50	4		T45	6
valid_sources[0x1d]	223	1		T69	3		T50	2		T45	4
valid_sources[0x1e]	74	1		T69	2		T50	6		T45	1
valid_sources[0x1f]	134	1		T69	1		T50	4		T43	8
valid_sources[0x20]	60	1		T53	2		T69	3		T64	2
valid_sources[0x21]	114	1		T141	1		T69	5		T50	2
valid_sources[0x22]	58	1		T69	4		T50	6		T64	1
valid_sources[0x23]	43	1		T53	3		T45	1		T64	1
valid_sources[0x24]	33	1		T137	1		T131	2		T50	1
valid_sources[0x25]	152	1		T140	2		T141	1		T45	1
valid_sources[0x26]	56	1		T45	2		T64	1		T79	2
valid_sources[0x27]	46	1		T53	1		T138	1		T45	1
valid_sources[0x28]	50	1		T145	1		T69	2		T50	10
valid_sources[0x29]	49	1		T69	2		T50	12		T45	1
valid_sources[0x2a]	52	1		T69	1		T50	2		T45	7
valid_sources[0x2b]	127	1		T69	2		T45	1		T64	2
valid_sources[0x2c]	77	1		T146	19		T64	2		T84	1
valid_sources[0x2d]	104	1		T42	1		T78	49		T89	5
valid_sources[0x2e]	40	1		T137	1		T142	1		T64	1
valid_sources[0x2f]	46	1		T87	2		T69	3		T64	1
valid_sources[0x30]	33	1		T143	1		T64	1		T84	1
valid_sources[0x31]	193	1		T69	2		T58	44		T84	3
valid_sources[0x32]	61	1		T144	1		T143	1		T48	2
valid_sources[0x33]	82	1		T147	1		T69	1		T50	1
valid_sources[0x34]	58	1		T132	1		T50	3		T45	1
valid_sources[0x35]	56	1		T137	2		T69	1		T50	4
valid_sources[0x36]	73	1		T138	1		T50	1		T64	4
valid_sources[0x37]	106	1		T45	1		T64	2		T46	5
valid_sources[0x38]	45	1		T53	3		T69	3		T50	1
valid_sources[0x39]	100	1		T2	2		T148	11		T149	13
valid_sources[0x3a]	75	1		T69	1		T50	6		T45	2
valid_sources[0x3b]	68	1		T58	5		T45	8		T79	1
valid_sources[0x3c]	73	1		T147	1		T69	3		T50	3
valid_sources[0x3d]	53	1		T3	1		T53	1		T135	2
valid_sources[0x3e]	64	1		T138	1		T69	14		T45	3
valid_sources[0x3f]	65	1		T36	1		T30	1		T150	1
valid_sources[0x40]	106	1		T69	1		T45	2		T64	1
valid_sources[0x41]	74	1		T3	3		T142	1		T50	6
valid_sources[0x42]	206	1		T69	1		T42	1		T45	1
valid_sources[0x43]	114	1		T69	3		T45	4		T77	1
valid_sources[0x44]	33	1		T151	1		T64	1		T88	2
valid_sources[0x45]	82	1		T152	18		T144	1		T50	8
valid_sources[0x46]	85	1		T138	4		T134	1		T50	1
valid_sources[0x47]	42	1		T72	1		T153	1		T50	5
valid_sources[0x48]	35	1		T69	1		T45	2		T84	2
valid_sources[0x49]	66	1		T132	1		T50	1		T42	1
valid_sources[0x4a]	84	1		T138	1		T43	7		T64	4
valid_sources[0x4b]	75	1		T151	1		T45	1		T64	3
valid_sources[0x4c]	46	1		T64	1		T84	3		T46	1
valid_sources[0x4d]	60	1		T50	2		T43	1		T46	5
valid_sources[0x4e]	64	1		T69	1		T50	8		T64	2
valid_sources[0x4f]	68	1		T45	3		T64	1		T46	10
valid_sources[0x50]	60	1		T69	3		T50	7		T45	1
valid_sources[0x51]	52	1		T154	3		T132	1		T69	7
valid_sources[0x52]	52	1		T2	1		T150	1		T69	3
valid_sources[0x53]	68	1		T145	2		T64	2		T84	1
valid_sources[0x54]	65	1		T54	2		T69	8		T50	2
valid_sources[0x55]	47	1		T69	4		T50	2		T64	1
valid_sources[0x56]	53	1		T69	7		T50	1		T45	2
valid_sources[0x57]	87	1		T69	9		T50	2		T45	3
valid_sources[0x58]	55	1		T140	1		T155	2		T69	1
valid_sources[0x59]	62	1		T141	1		T69	1		T50	3
valid_sources[0x5a]	68	1		T50	7		T64	3		T46	6
valid_sources[0x5b]	53	1		T69	6		T45	13		T64	2
valid_sources[0x5c]	87	1		T30	1		T154	2		T64	3
valid_sources[0x5d]	37	1		T133	2		T143	1		T69	3
valid_sources[0x5e]	55	1		T50	3		T58	3		T45	3
valid_sources[0x5f]	58	1		T50	4		T45	3		T64	2
valid_sources[0x60]	56	1		T131	1		T50	5		T64	2
valid_sources[0x61]	138	1		T145	1		T144	1		T147	1
valid_sources[0x62]	53	1		T69	5		T50	7		T42	1
valid_sources[0x63]	60	1		T53	1		T143	1		T50	5
valid_sources[0x64]	54	1		T36	1		T69	1		T50	1
valid_sources[0x65]	38	1		T144	1		T50	1		T45	4
valid_sources[0x66]	265	1		T145	1		T135	1		T45	1
valid_sources[0x67]	48	1		T1	1		T69	1		T50	3
valid_sources[0x68]	40	1		T64	1		T84	1		T46	1
valid_sources[0x69]	54	1		T2	1		T69	4		T88	4
valid_sources[0x6a]	95	1		T69	4		T45	3		T64	3
valid_sources[0x6b]	55	1		T147	1		T69	4		T50	7
valid_sources[0x6c]	93	1		T69	4		T45	6		T84	1
valid_sources[0x6d]	69	1		T54	2		T150	1		T48	1
valid_sources[0x6e]	76	1		T54	1		T43	1		T84	3
valid_sources[0x6f]	47	1		T134	2		T45	5		T64	1
valid_sources[0x70]	52	1		T42	2		T64	1		T88	3
valid_sources[0x71]	45	1		T141	1		T69	7		T45	3
valid_sources[0x72]	60	1		T69	3		T89	4		T156	1
valid_sources[0x73]	44	1		T50	1		T45	1		T64	2
valid_sources[0x74]	203	1		T38	8		T53	2		T72	1
valid_sources[0x75]	55	1		T53	3		T155	1		T69	10
valid_sources[0x76]	48	1		T150	1		T69	2		T50	7
valid_sources[0x77]	80	1		T144	1		T64	1		T44	2
valid_sources[0x78]	46	1		T69	4		T46	6		T80	1
valid_sources[0x79]	41	1		T138	1		T64	2		T47	3
valid_sources[0x7a]	50	1		T69	8		T64	2		T46	2
valid_sources[0x7b]	81	1		T69	5		T50	2		T45	5
valid_sources[0x7c]	114	1		T137	1		T154	2		T50	11
valid_sources[0x7d]	76	1		T69	6		T50	9		T64	4
valid_sources[0x7e]	118	1		T153	3		T64	2		T84	1
valid_sources[0x7f]	51	1		T141	1		T50	4		T45	1
valid_sources[0x80]	62	1		T30	1		T69	3		T50	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4856

1

T48

1

T69

157

T50

167

values[0x0]

all_enables

biggest_size

6159

1

T2

3

T3

2

T36

1

values[0x1]

all_enables

biggest_size

6157

1

T1

2

T2

3

T51

1