Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	187109	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	540255	1		T4	7		T5	32		T7	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	441641	1		T5	4		T35	8		T15	39
values[0x0]	141234	1		T4	15		T5	42		T7	5
values[0x1]	144489	1		T4	8		T5	59		T7	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	144889	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	582475	1		T4	8		T5	45		T7	2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3130	1		T6	1		T50	2		T47	3
valid_sources[0x01]	3274	1		T71	1		T82	2		T30	5
valid_sources[0x02]	2928	1		T80	1		T47	1		T48	5
valid_sources[0x03]	2714	1		T41	1		T47	2		T48	7
valid_sources[0x04]	2515	1		T15	1		T80	1		T47	2
valid_sources[0x05]	2720	1		T10	1		T46	1		T82	8
valid_sources[0x06]	3066	1		T6	1		T47	2		T48	6
valid_sources[0x07]	3128	1		T6	2		T80	1		T138	2
valid_sources[0x08]	2928	1		T64	7		T50	1		T47	3
valid_sources[0x09]	2582	1		T80	1		T139	1		T50	1
valid_sources[0x0a]	2868	1		T80	2		T47	3		T48	9
valid_sources[0x0b]	2437	1		T6	1		T10	2		T82	5
valid_sources[0x0c]	2715	1		T6	1		T16	1		T138	1
valid_sources[0x0d]	3507	1		T6	2		T80	3		T10	1
valid_sources[0x0e]	2714	1		T15	8		T50	2		T47	5
valid_sources[0x0f]	2731	1		T6	1		T80	1		T12	1
valid_sources[0x10]	3274	1		T50	1		T48	9		T51	13
valid_sources[0x11]	2596	1		T16	4		T80	1		T46	1
valid_sources[0x12]	2664	1		T6	2		T80	1		T50	2
valid_sources[0x13]	3078	1		T80	1		T41	1		T47	2
valid_sources[0x14]	3319	1		T4	1		T6	1		T10	1
valid_sources[0x15]	2748	1		T7	1		T6	2		T32	5
valid_sources[0x16]	2701	1		T50	1		T47	5		T48	9
valid_sources[0x17]	2589	1		T6	1		T50	3		T47	9
valid_sources[0x18]	2868	1		T33	1		T47	5		T48	8
valid_sources[0x19]	3524	1		T80	1		T140	5		T47	4
valid_sources[0x1a]	2401	1		T82	6		T47	8		T48	6
valid_sources[0x1b]	2865	1		T12	1		T50	5		T47	4
valid_sources[0x1c]	2784	1		T23	4		T10	2		T81	1
valid_sources[0x1d]	2744	1		T15	6		T47	5		T48	8
valid_sources[0x1e]	2961	1		T15	8		T141	2		T138	6
valid_sources[0x1f]	3409	1		T35	1		T80	1		T46	2
valid_sources[0x20]	2576	1		T6	1		T50	1		T47	2
valid_sources[0x21]	2621	1		T15	12		T80	1		T47	5
valid_sources[0x22]	2778	1		T16	2		T50	2		T47	1
valid_sources[0x23]	2408	1		T6	1		T72	2		T33	2
valid_sources[0x24]	3401	1		T41	2		T138	1		T47	9
valid_sources[0x25]	2904	1		T50	3		T47	3		T48	13
valid_sources[0x26]	2641	1		T15	10		T80	2		T47	3
valid_sources[0x27]	2935	1		T50	1		T47	9		T48	6
valid_sources[0x28]	2708	1		T50	1		T47	1		T48	5
valid_sources[0x29]	2618	1		T71	2		T30	27		T50	4
valid_sources[0x2a]	2624	1		T6	1		T16	7		T10	9
valid_sources[0x2b]	2575	1		T50	3		T47	1		T48	13
valid_sources[0x2c]	2751	1		T16	1		T64	3		T47	2
valid_sources[0x2d]	2497	1		T6	1		T50	1		T48	6
valid_sources[0x2e]	2354	1		T138	1		T50	2		T47	2
valid_sources[0x2f]	2639	1		T138	2		T50	3		T47	3
valid_sources[0x30]	2559	1		T6	1		T10	1		T46	4
valid_sources[0x31]	3016	1		T139	1		T50	4		T47	4
valid_sources[0x32]	3558	1		T6	3		T32	16		T50	3
valid_sources[0x33]	2964	1		T6	1		T80	1		T82	1
valid_sources[0x34]	2759	1		T16	2		T81	1		T47	2
valid_sources[0x35]	2683	1		T16	1		T80	1		T32	19
valid_sources[0x36]	3045	1		T6	1		T33	1		T139	2
valid_sources[0x37]	2718	1		T6	1		T50	2		T48	7
valid_sources[0x38]	3056	1		T80	1		T46	6		T50	2
valid_sources[0x39]	3745	1		T82	7		T50	2		T47	2
valid_sources[0x3a]	2802	1		T47	1		T48	8		T51	14
valid_sources[0x3b]	2863	1		T6	3		T46	5		T41	2
valid_sources[0x3c]	2879	1		T6	1		T80	2		T47	4
valid_sources[0x3d]	3018	1		T6	1		T36	9		T139	6
valid_sources[0x3e]	2702	1		T15	1		T80	1		T33	1
valid_sources[0x3f]	2769	1		T46	10		T33	1		T32	1
valid_sources[0x40]	2552	1		T64	3		T30	4		T47	5
valid_sources[0x41]	2349	1		T33	1		T47	2		T48	7
valid_sources[0x42]	2727	1		T6	1		T50	2		T47	4
valid_sources[0x43]	2630	1		T6	1		T50	1		T47	6
valid_sources[0x44]	2265	1		T6	1		T35	1		T80	1
valid_sources[0x45]	2895	1		T16	5		T64	3		T30	8
valid_sources[0x46]	2998	1		T6	1		T48	7		T51	15
valid_sources[0x47]	2631	1		T6	1		T50	3		T47	5
valid_sources[0x48]	3020	1		T6	2		T41	2		T139	1
valid_sources[0x49]	2702	1		T6	1		T80	1		T139	2
valid_sources[0x4a]	2742	1		T15	2		T47	2		T51	11
valid_sources[0x4b]	3065	1		T7	1		T15	8		T16	6
valid_sources[0x4c]	2947	1		T7	1		T41	1		T50	2
valid_sources[0x4d]	3143	1		T16	7		T48	9		T51	7
valid_sources[0x4e]	2689	1		T80	2		T10	2		T64	1
valid_sources[0x4f]	2865	1		T82	7		T41	1		T50	2
valid_sources[0x50]	2799	1		T15	5		T80	1		T139	4
valid_sources[0x51]	3055	1		T80	1		T10	2		T32	4
valid_sources[0x52]	3307	1		T6	1		T138	3		T47	1
valid_sources[0x53]	2941	1		T41	1		T50	2		T47	3
valid_sources[0x54]	3417	1		T6	1		T80	3		T142	1
valid_sources[0x55]	3102	1		T4	3		T35	1		T143	49
valid_sources[0x56]	3093	1		T80	1		T41	5		T64	5
valid_sources[0x57]	2720	1		T34	1		T32	4		T50	1
valid_sources[0x58]	2667	1		T16	3		T64	3		T144	12
valid_sources[0x59]	3138	1		T80	1		T47	2		T48	7
valid_sources[0x5a]	3202	1		T80	2		T47	2		T48	8
valid_sources[0x5b]	2846	1		T16	4		T80	1		T47	3
valid_sources[0x5c]	2616	1		T41	1		T47	4		T48	8
valid_sources[0x5d]	3285	1		T80	2		T47	1		T48	5
valid_sources[0x5e]	2310	1		T16	1		T10	8		T64	3
valid_sources[0x5f]	2467	1		T16	4		T80	1		T138	11
valid_sources[0x60]	2657	1		T6	1		T47	6		T48	12
valid_sources[0x61]	2510	1		T7	1		T47	4		T48	5
valid_sources[0x62]	2289	1		T16	4		T64	2		T47	2
valid_sources[0x63]	3108	1		T6	1		T15	11		T142	1
valid_sources[0x64]	2934	1		T15	2		T23	3		T141	2
valid_sources[0x65]	2950	1		T15	1		T80	3		T64	2
valid_sources[0x66]	3000	1		T7	1		T80	1		T47	1
valid_sources[0x67]	2725	1		T6	3		T140	1		T50	4
valid_sources[0x68]	2636	1		T80	2		T81	1		T41	3
valid_sources[0x69]	2496	1		T80	2		T10	1		T138	7
valid_sources[0x6a]	2129	1		T80	1		T50	2		T47	4
valid_sources[0x6b]	3038	1		T80	2		T50	1		T47	1
valid_sources[0x6c]	2155	1		T47	1		T48	13		T51	9
valid_sources[0x6d]	2984	1		T6	1		T80	2		T81	1
valid_sources[0x6e]	2418	1		T6	2		T80	2		T10	3
valid_sources[0x6f]	3037	1		T6	1		T72	2		T80	1
valid_sources[0x70]	2392	1		T4	3		T72	1		T41	1
valid_sources[0x71]	3086	1		T50	1		T47	5		T48	3
valid_sources[0x72]	2477	1		T10	2		T138	1		T50	1
valid_sources[0x73]	2406	1		T50	2		T47	11		T48	4
valid_sources[0x74]	2430	1		T16	3		T139	1		T47	3
valid_sources[0x75]	3314	1		T16	2		T80	1		T50	2
valid_sources[0x76]	3457	1		T16	2		T80	1		T50	2
valid_sources[0x77]	2591	1		T4	2		T10	7		T64	2
valid_sources[0x78]	2707	1		T10	2		T64	3		T139	3
valid_sources[0x79]	2508	1		T16	2		T10	1		T50	1
valid_sources[0x7a]	3008	1		T16	2		T80	4		T41	2
valid_sources[0x7b]	2643	1		T15	2		T72	2		T50	2
valid_sources[0x7c]	3556	1		T6	1		T80	1		T47	1
valid_sources[0x7d]	2683	1		T6	1		T10	3		T50	1
valid_sources[0x7e]	2578	1		T10	4		T50	6		T47	2
valid_sources[0x7f]	2724	1		T16	5		T50	2		T47	2
valid_sources[0x80]	2681	1		T50	1		T47	3		T48	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

262862

1

T5

2

T35

3

T15

18

values[0x0]

all_enables

biggest_size

139119

1

T4

6

T5

17

T7

1

values[0x1]

all_enables

biggest_size

138274

1

T4

1

T5

13

T7

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4670	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	18781	1		T1	4		T25	4		T26	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9116	1		T50	202		T47	33		T48	54
values[0x0]	6944	1		T1	6		T25	5		T26	4
values[0x1]	7391	1		T1	6		T25	5		T26	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3624	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	19827	1		T1	5		T25	4		T26	3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50	1		T76	3		T101	1		T62	1
valid_sources[0x01]	95	1		T145	1		T146	1		T147	6
valid_sources[0x02]	58	1		T148	1		T50	2		T48	2
valid_sources[0x03]	79	1		T149	1		T50	3		T48	1
valid_sources[0x04]	84	1		T26	1		T149	3		T50	2
valid_sources[0x05]	74	1		T150	1		T50	3		T48	1
valid_sources[0x06]	54	1		T50	1		T85	8		T88	1
valid_sources[0x07]	74	1		T50	3		T48	1		T76	2
valid_sources[0x08]	64	1		T76	2		T101	3		T95	2
valid_sources[0x09]	68	1		T151	2		T48	1		T75	1
valid_sources[0x0a]	178	1		T25	1		T50	1		T48	1
valid_sources[0x0b]	80	1		T50	1		T48	2		T76	1
valid_sources[0x0c]	74	1		T50	4		T48	1		T85	1
valid_sources[0x0d]	55	1		T60	1		T50	2		T49	2
valid_sources[0x0e]	118	1		T152	1		T50	4		T68	1
valid_sources[0x0f]	83	1		T50	3		T48	1		T51	1
valid_sources[0x10]	73	1		T50	2		T68	2		T79	1
valid_sources[0x11]	61	1		T50	7		T49	2		T88	1
valid_sources[0x12]	67	1		T50	1		T85	1		T76	1
valid_sources[0x13]	73	1		T50	2		T48	1		T87	2
valid_sources[0x14]	77	1		T50	1		T68	5		T76	2
valid_sources[0x15]	62	1		T50	2		T48	2		T51	1
valid_sources[0x16]	351	1		T150	1		T50	3		T67	3
valid_sources[0x17]	67	1		T50	1		T48	3		T85	2
valid_sources[0x18]	92	1		T26	1		T50	6		T68	1
valid_sources[0x19]	79	1		T53	1		T50	1		T48	1
valid_sources[0x1a]	154	1		T50	2		T48	1		T68	1
valid_sources[0x1b]	80	1		T73	1		T48	1		T86	4
valid_sources[0x1c]	66	1		T153	1		T50	3		T48	3
valid_sources[0x1d]	166	1		T58	15		T154	1		T50	5
valid_sources[0x1e]	87	1		T50	1		T51	1		T85	1
valid_sources[0x1f]	72	1		T25	1		T50	3		T85	1
valid_sources[0x20]	62	1		T50	3		T49	1		T68	2
valid_sources[0x21]	52	1		T50	3		T48	2		T49	1
valid_sources[0x22]	59	1		T155	1		T149	1		T50	2
valid_sources[0x23]	227	1		T147	4		T50	9		T48	1
valid_sources[0x24]	123	1		T50	2		T48	1		T85	1
valid_sources[0x25]	87	1		T156	1		T50	4		T48	2
valid_sources[0x26]	85	1		T157	1		T50	3		T48	1
valid_sources[0x27]	64	1		T57	1		T73	2		T146	1
valid_sources[0x28]	56	1		T145	1		T49	1		T85	1
valid_sources[0x29]	90	1		T50	5		T48	2		T67	2
valid_sources[0x2a]	255	1		T50	3		T48	2		T85	5
valid_sources[0x2b]	111	1		T48	2		T49	1		T85	2
valid_sources[0x2c]	75	1		T50	2		T76	2		T99	2
valid_sources[0x2d]	80	1		T158	9		T50	2		T85	4
valid_sources[0x2e]	91	1		T146	2		T159	6		T50	2
valid_sources[0x2f]	185	1		T160	5		T50	3		T48	3
valid_sources[0x30]	94	1		T50	2		T85	3		T68	3
valid_sources[0x31]	98	1		T153	1		T50	5		T68	1
valid_sources[0x32]	108	1		T161	2		T152	1		T150	1
valid_sources[0x33]	78	1		T117	16		T50	1		T85	2
valid_sources[0x34]	106	1		T50	3		T68	2		T76	2
valid_sources[0x35]	88	1		T162	8		T50	2		T48	1
valid_sources[0x36]	108	1		T163	13		T85	5		T76	4
valid_sources[0x37]	92	1		T50	6		T48	2		T85	8
valid_sources[0x38]	112	1		T148	1		T159	2		T164	5
valid_sources[0x39]	180	1		T165	1		T156	1		T50	5
valid_sources[0x3a]	75	1		T50	3		T85	3		T68	1
valid_sources[0x3b]	79	1		T50	4		T84	3		T68	1
valid_sources[0x3c]	61	1		T50	2		T48	1		T76	5
valid_sources[0x3d]	122	1		T26	1		T73	2		T150	1
valid_sources[0x3e]	78	1		T25	2		T165	1		T50	1
valid_sources[0x3f]	90	1		T60	1		T50	3		T48	1
valid_sources[0x40]	109	1		T148	2		T50	2		T48	1
valid_sources[0x41]	65	1		T60	1		T166	6		T68	1
valid_sources[0x42]	73	1		T48	1		T85	1		T68	2
valid_sources[0x43]	134	1		T148	1		T50	2		T48	1
valid_sources[0x44]	76	1		T50	3		T48	1		T49	1
valid_sources[0x45]	59	1		T50	1		T48	2		T77	1
valid_sources[0x46]	69	1		T50	5		T85	2		T68	1
valid_sources[0x47]	68	1		T50	3		T68	2		T76	3
valid_sources[0x48]	296	1		T50	2		T47	6		T48	3
valid_sources[0x49]	49	1		T53	1		T48	1		T88	1
valid_sources[0x4a]	76	1		T50	3		T51	1		T76	3
valid_sources[0x4b]	71	1		T47	2		T68	1		T76	2
valid_sources[0x4c]	79	1		T50	4		T48	1		T85	7
valid_sources[0x4d]	96	1		T151	1		T167	5		T50	2
valid_sources[0x4e]	120	1		T152	1		T50	4		T48	2
valid_sources[0x4f]	179	1		T70	7		T168	1		T50	2
valid_sources[0x50]	56	1		T50	3		T48	1		T76	1
valid_sources[0x51]	97	1		T149	1		T50	3		T48	1
valid_sources[0x52]	52	1		T60	1		T50	1		T48	2
valid_sources[0x53]	76	1		T26	1		T50	3		T49	2
valid_sources[0x54]	109	1		T50	6		T48	3		T87	2
valid_sources[0x55]	80	1		T50	5		T48	3		T76	1
valid_sources[0x56]	72	1		T145	1		T169	1		T50	7
valid_sources[0x57]	61	1		T25	1		T146	1		T76	5
valid_sources[0x58]	74	1		T1	1		T26	1		T50	6
valid_sources[0x59]	90	1		T151	1		T50	9		T76	4
valid_sources[0x5a]	70	1		T53	1		T165	1		T153	2
valid_sources[0x5b]	84	1		T50	8		T48	1		T84	6
valid_sources[0x5c]	130	1		T145	1		T152	1		T50	3
valid_sources[0x5d]	102	1		T50	2		T85	1		T87	3
valid_sources[0x5e]	95	1		T151	2		T165	1		T50	3
valid_sources[0x5f]	77	1		T170	9		T153	1		T50	2
valid_sources[0x60]	113	1		T50	5		T85	2		T68	4
valid_sources[0x61]	78	1		T171	2		T167	2		T50	3
valid_sources[0x62]	194	1		T149	1		T50	1		T85	1
valid_sources[0x63]	55	1		T50	1		T48	1		T68	3
valid_sources[0x64]	115	1		T50	7		T48	1		T85	1
valid_sources[0x65]	81	1		T50	5		T85	4		T68	1
valid_sources[0x66]	55	1		T50	6		T51	1		T76	2
valid_sources[0x67]	81	1		T57	1		T172	7		T50	4
valid_sources[0x68]	55	1		T50	4		T48	1		T85	2
valid_sources[0x69]	157	1		T50	4		T48	2		T85	1
valid_sources[0x6a]	165	1		T151	1		T161	5		T50	3
valid_sources[0x6b]	132	1		T145	1		T167	2		T50	1
valid_sources[0x6c]	54	1		T168	1		T50	2		T76	2
valid_sources[0x6d]	66	1		T156	1		T50	1		T49	2
valid_sources[0x6e]	130	1		T50	1		T85	7		T76	4
valid_sources[0x6f]	82	1		T50	3		T48	1		T49	1
valid_sources[0x70]	97	1		T1	2		T50	3		T85	2
valid_sources[0x71]	110	1		T50	1		T48	2		T85	3
valid_sources[0x72]	61	1		T167	2		T50	3		T49	1
valid_sources[0x73]	60	1		T153	1		T50	1		T68	1
valid_sources[0x74]	87	1		T50	2		T68	2		T76	3
valid_sources[0x75]	248	1		T151	1		T173	3		T50	4
valid_sources[0x76]	71	1		T174	5		T50	3		T48	2
valid_sources[0x77]	116	1		T50	6		T49	1		T85	4
valid_sources[0x78]	84	1		T175	3		T50	6		T68	3
valid_sources[0x79]	191	1		T50	2		T85	10		T89	1
valid_sources[0x7a]	86	1		T50	4		T51	1		T68	1
valid_sources[0x7b]	73	1		T50	5		T76	5		T95	1
valid_sources[0x7c]	212	1		T50	4		T85	5		T76	3
valid_sources[0x7d]	64	1		T159	2		T50	3		T51	1
valid_sources[0x7e]	98	1		T154	1		T50	1		T85	1
valid_sources[0x7f]	73	1		T176	1		T50	4		T48	1
valid_sources[0x80]	71	1		T50	2		T85	1		T76	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6384

1

T50

193

T47

28

T48

48

values[0x0]

all_enables

biggest_size

6210

1

T1

2

T25

3

T26

2

values[0x1]

all_enables

biggest_size

6187

1

T1

2

T25

1

T58

1