Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	220126	1		T4	16		T5	73		T7	6
full_word	541610	1		T4	7		T5	32		T7	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	761456	1		T4	23		T5	105		T7	8
auto[TlIntgErrCmd]	92	1		T67	5		T77	2		T119	1
auto[TlIntgErrData]	95	1		T67	2		T77	4		T119	4
auto[TlIntgErrBoth]	93	1		T67	3		T77	4		T119	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	443289	1		T5	4		T35	8		T15	39
auto[1]	318447	1		T4	23		T5	101		T7	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	180136	1		T5	2		T35	5		T15	21
auto[TlIntgErrNone]	partial	auto[1]	39737	1		T4	16		T5	71		T7	6
auto[TlIntgErrNone]	full_word	auto[0]	263025	1		T5	2		T35	3		T15	18
auto[TlIntgErrNone]	full_word	auto[1]	278558	1		T4	7		T5	30		T7	2
auto[TlIntgErrCmd]	partial	auto[0]	39	1		T67	2		T77	1		T124	2
auto[TlIntgErrCmd]	partial	auto[1]	42	1		T67	3		T77	1		T119	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T131	1		T132	1		T133	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T124	2		T125	1		T131	1
auto[TlIntgErrData]	partial	auto[0]	44	1		T67	1		T77	3		T119	2
auto[TlIntgErrData]	partial	auto[1]	44	1		T67	1		T119	2		T124	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T126	1		T134	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1		T77	1		T125	1		T133	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1		T67	2		T77	2		T119	1
auto[TlIntgErrBoth]	partial	auto[1]	49	1		T67	1		T77	2		T119	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T119	1		T124	1		T135	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T119	2		T129	2		T136	1