Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201990	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	524851	1		T2	100		T3	2		T4	11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	479709	1		T2	97		T15	16		T8	42
values[0x0]	121492	1		T2	53		T4	28		T6	8
values[0x1]	125640	1		T2	69		T3	2		T4	45

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	152196	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	574645	1		T2	118		T3	2		T4	18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6375	1		T120	1		T36	16		T31	24
valid_sources[0x01]	2757	1		T4	2		T15	1		T36	9
valid_sources[0x02]	2805	1		T29	1		T34	1		T31	20
valid_sources[0x03]	3740	1		T5	1		T34	3		T31	21
valid_sources[0x04]	2528	1		T29	1		T36	8		T31	8
valid_sources[0x05]	2794	1		T120	1		T54	5		T36	18
valid_sources[0x06]	2797	1		T31	27		T37	17		T35	4
valid_sources[0x07]	2486	1		T8	1		T17	248		T29	1
valid_sources[0x08]	4556	1		T86	5		T54	2		T29	1
valid_sources[0x09]	2791	1		T36	5		T34	2		T31	20
valid_sources[0x0a]	2483	1		T5	2		T8	3		T36	23
valid_sources[0x0b]	2997	1		T4	2		T8	1		T120	1
valid_sources[0x0c]	2700	1		T8	3		T54	1		T36	32
valid_sources[0x0d]	2593	1		T120	1		T36	10		T31	20
valid_sources[0x0e]	3016	1		T4	1		T36	24		T31	16
valid_sources[0x0f]	2982	1		T36	16		T34	3		T31	8
valid_sources[0x10]	2531	1		T29	1		T36	11		T31	13
valid_sources[0x11]	2815	1		T34	1		T31	26		T37	29
valid_sources[0x12]	2744	1		T4	1		T36	1		T34	1
valid_sources[0x13]	2351	1		T36	19		T31	19		T37	11
valid_sources[0x14]	2686	1		T120	2		T36	31		T31	19
valid_sources[0x15]	3448	1		T29	1		T31	16		T37	27
valid_sources[0x16]	2397	1		T6	1		T31	15		T37	13
valid_sources[0x17]	3197	1		T15	1		T135	1		T36	8
valid_sources[0x18]	3044	1		T8	1		T31	20		T37	7
valid_sources[0x19]	2783	1		T6	1		T135	1		T29	1
valid_sources[0x1a]	2589	1		T15	3		T31	19		T37	24
valid_sources[0x1b]	2572	1		T4	2		T15	1		T54	2
valid_sources[0x1c]	2601	1		T36	17		T34	2		T31	39
valid_sources[0x1d]	2715	1		T8	4		T31	48		T37	20
valid_sources[0x1e]	2665	1		T4	1		T15	1		T29	2
valid_sources[0x1f]	2376	1		T8	2		T54	9		T34	1
valid_sources[0x20]	2895	1		T36	48		T34	1		T31	37
valid_sources[0x21]	3133	1		T8	1		T36	36		T31	18
valid_sources[0x22]	2674	1		T14	1		T8	2		T36	14
valid_sources[0x23]	2432	1		T120	1		T86	1		T36	31
valid_sources[0x24]	2800	1		T120	1		T36	7		T31	35
valid_sources[0x25]	2427	1		T15	1		T8	3		T136	1
valid_sources[0x26]	2889	1		T4	1		T120	1		T34	2
valid_sources[0x27]	2424	1		T31	43		T37	14		T35	5
valid_sources[0x28]	2896	1		T36	30		T34	1		T31	53
valid_sources[0x29]	2577	1		T4	1		T8	2		T59	1
valid_sources[0x2a]	2554	1		T36	18		T31	18		T37	19
valid_sources[0x2b]	2762	1		T120	1		T36	10		T31	30
valid_sources[0x2c]	2540	1		T36	15		T31	25		T37	14
valid_sources[0x2d]	2974	1		T36	11		T34	1		T31	13
valid_sources[0x2e]	2616	1		T59	1		T29	1		T36	10
valid_sources[0x2f]	4160	1		T135	1		T36	37		T31	23
valid_sources[0x30]	2907	1		T8	1		T135	1		T36	58
valid_sources[0x31]	2617	1		T8	2		T36	31		T31	18
valid_sources[0x32]	2820	1		T36	13		T31	27		T37	3
valid_sources[0x33]	2479	1		T5	1		T137	7		T34	2
valid_sources[0x34]	3003	1		T34	1		T31	20		T37	55
valid_sources[0x35]	2562	1		T135	1		T36	9		T31	7
valid_sources[0x36]	3194	1		T4	3		T34	1		T31	29
valid_sources[0x37]	2605	1		T29	2		T137	1		T36	3
valid_sources[0x38]	2404	1		T5	1		T54	3		T36	12
valid_sources[0x39]	2860	1		T8	4		T54	6		T29	3
valid_sources[0x3a]	2590	1		T15	1		T120	1		T29	2
valid_sources[0x3b]	2732	1		T4	1		T15	3		T29	1
valid_sources[0x3c]	2446	1		T15	1		T14	1		T34	1
valid_sources[0x3d]	2356	1		T4	1		T15	1		T36	19
valid_sources[0x3e]	2431	1		T9	22		T29	1		T36	2
valid_sources[0x3f]	2395	1		T8	1		T36	1		T34	2
valid_sources[0x40]	2808	1		T36	8		T31	15		T37	22
valid_sources[0x41]	2587	1		T120	1		T59	1		T86	1
valid_sources[0x42]	3151	1		T9	48		T86	12		T135	1
valid_sources[0x43]	2680	1		T4	2		T54	3		T36	29
valid_sources[0x44]	2388	1		T4	1		T5	1		T34	1
valid_sources[0x45]	2718	1		T8	2		T29	1		T137	2
valid_sources[0x46]	3025	1		T120	1		T137	1		T36	1
valid_sources[0x47]	2660	1		T15	1		T135	1		T36	13
valid_sources[0x48]	2356	1		T60	2		T29	2		T137	1
valid_sources[0x49]	2515	1		T59	1		T36	23		T34	1
valid_sources[0x4a]	2252	1		T4	1		T86	1		T34	1
valid_sources[0x4b]	4098	1		T87	12		T137	1		T136	1
valid_sources[0x4c]	2676	1		T6	1		T137	3		T36	49
valid_sources[0x4d]	2789	1		T36	21		T31	19		T37	15
valid_sources[0x4e]	2702	1		T4	2		T29	1		T34	1
valid_sources[0x4f]	2797	1		T137	5		T36	24		T34	1
valid_sources[0x50]	2921	1		T29	1		T36	28		T31	15
valid_sources[0x51]	2690	1		T8	1		T9	4		T56	3
valid_sources[0x52]	2408	1		T9	19		T36	8		T34	1
valid_sources[0x53]	2234	1		T36	16		T34	1		T31	10
valid_sources[0x54]	2571	1		T4	1		T31	20		T37	27
valid_sources[0x55]	4308	1		T15	1		T135	1		T31	20
valid_sources[0x56]	2679	1		T120	1		T54	1		T135	1
valid_sources[0x57]	2275	1		T36	31		T34	2		T31	20
valid_sources[0x58]	2513	1		T5	2		T29	1		T36	33
valid_sources[0x59]	2481	1		T29	2		T36	13		T31	17
valid_sources[0x5a]	3761	1		T34	2		T31	18		T37	14
valid_sources[0x5b]	3324	1		T54	1		T31	28		T37	27
valid_sources[0x5c]	2487	1		T4	1		T45	2		T137	2
valid_sources[0x5d]	4186	1		T8	1		T120	1		T55	80
valid_sources[0x5e]	2576	1		T4	2		T8	2		T36	8
valid_sources[0x5f]	2536	1		T5	2		T8	3		T29	1
valid_sources[0x60]	2527	1		T9	2		T34	1		T31	38
valid_sources[0x61]	2433	1		T15	1		T29	2		T34	3
valid_sources[0x62]	2302	1		T29	1		T137	6		T36	10
valid_sources[0x63]	2547	1		T9	1		T36	38		T31	34
valid_sources[0x64]	2579	1		T2	219		T4	1		T15	2
valid_sources[0x65]	2576	1		T15	2		T5	3		T29	1
valid_sources[0x66]	3233	1		T36	15		T31	27		T37	34
valid_sources[0x67]	2422	1		T8	3		T137	7		T34	1
valid_sources[0x68]	2871	1		T5	1		T29	1		T34	1
valid_sources[0x69]	2803	1		T5	1		T36	22		T34	1
valid_sources[0x6a]	2797	1		T5	1		T8	4		T36	18
valid_sources[0x6b]	2585	1		T14	2		T31	29		T37	21
valid_sources[0x6c]	2905	1		T15	1		T8	1		T31	24
valid_sources[0x6d]	2526	1		T120	1		T29	1		T137	3
valid_sources[0x6e]	2495	1		T4	1		T8	1		T36	25
valid_sources[0x6f]	2497	1		T4	2		T29	1		T34	1
valid_sources[0x70]	2770	1		T4	1		T5	2		T36	3
valid_sources[0x71]	2570	1		T120	1		T22	33		T138	73
valid_sources[0x72]	2308	1		T4	3		T6	1		T34	3
valid_sources[0x73]	2666	1		T137	2		T36	18		T34	2
valid_sources[0x74]	2701	1		T120	1		T137	3		T36	8
valid_sources[0x75]	2473	1		T120	1		T29	1		T36	12
valid_sources[0x76]	2611	1		T6	1		T8	2		T120	2
valid_sources[0x77]	2857	1		T8	2		T36	40		T31	11
valid_sources[0x78]	2514	1		T8	1		T135	1		T31	6
valid_sources[0x79]	2604	1		T36	49		T31	12		T37	45
valid_sources[0x7a]	2656	1		T29	1		T31	27		T37	35
valid_sources[0x7b]	3067	1		T8	2		T29	1		T36	1
valid_sources[0x7c]	2279	1		T135	1		T31	8		T37	48
valid_sources[0x7d]	2612	1		T4	1		T8	2		T36	15
valid_sources[0x7e]	2464	1		T8	5		T120	1		T29	2
valid_sources[0x7f]	2874	1		T5	1		T14	1		T137	3
valid_sources[0x80]	2951	1		T8	1		T29	2		T36	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

285231

1

T2

54

T15

7

T8

27

values[0x0]

all_enables

biggest_size

119787

1

T2

24

T4

5

T6

6

values[0x1]

all_enables

biggest_size

119833

1

T2

22

T3

2

T4

6

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4705	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	19019	1		T26	1		T27	4		T28	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9553	1		T36	23		T34	72		T31	35
values[0x0]	7007	1		T26	5		T27	6		T28	6
values[0x1]	7164	1		T26	5		T27	3		T28	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3582	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	20142	1		T26	2		T27	5		T28	4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	118	1		T119	1		T139	1		T35	2
valid_sources[0x01]	74	1		T52	7		T35	4		T81	6
valid_sources[0x02]	58	1		T140	1		T35	5		T32	1
valid_sources[0x03]	89	1		T74	10		T141	13		T36	1
valid_sources[0x04]	59	1		T142	8		T143	2		T34	1
valid_sources[0x05]	113	1		T34	2		T32	4		T33	15
valid_sources[0x06]	62	1		T35	2		T91	1		T85	1
valid_sources[0x07]	58	1		T34	1		T84	4		T85	4
valid_sources[0x08]	85	1		T35	3		T32	1		T81	3
valid_sources[0x09]	90	1		T144	1		T140	1		T34	3
valid_sources[0x0a]	123	1		T34	3		T35	3		T84	5
valid_sources[0x0b]	99	1		T36	3		T34	1		T35	4
valid_sources[0x0c]	82	1		T65	1		T145	4		T34	2
valid_sources[0x0d]	73	1		T146	1		T34	2		T35	4
valid_sources[0x0e]	103	1		T34	4		T35	1		T32	1
valid_sources[0x0f]	45	1		T147	1		T34	1		T35	1
valid_sources[0x10]	43	1		T73	2		T119	1		T36	1
valid_sources[0x11]	97	1		T71	6		T36	1		T35	4
valid_sources[0x12]	140	1		T34	1		T35	2		T85	5
valid_sources[0x13]	237	1		T34	2		T85	1		T92	1
valid_sources[0x14]	108	1		T34	1		T31	3		T35	2
valid_sources[0x15]	63	1		T75	1		T148	1		T34	1
valid_sources[0x16]	44	1		T34	1		T35	2		T85	2
valid_sources[0x17]	50	1		T34	3		T85	3		T92	2
valid_sources[0x18]	66	1		T34	1		T35	8		T32	1
valid_sources[0x19]	68	1		T149	1		T35	6		T32	1
valid_sources[0x1a]	75	1		T147	1		T150	2		T36	1
valid_sources[0x1b]	67	1		T151	2		T35	1		T84	4
valid_sources[0x1c]	49	1		T140	1		T34	2		T35	1
valid_sources[0x1d]	86	1		T75	3		T34	1		T35	6
valid_sources[0x1e]	61	1		T34	2		T35	3		T82	2
valid_sources[0x1f]	107	1		T75	1		T152	1		T34	3
valid_sources[0x20]	66	1		T26	1		T34	2		T35	2
valid_sources[0x21]	133	1		T34	2		T35	2		T85	2
valid_sources[0x22]	110	1		T147	1		T122	1		T34	4
valid_sources[0x23]	66	1		T35	4		T32	1		T85	4
valid_sources[0x24]	69	1		T26	1		T72	1		T34	2
valid_sources[0x25]	127	1		T51	1		T34	1		T85	1
valid_sources[0x26]	94	1		T36	1		T34	1		T33	3
valid_sources[0x27]	142	1		T27	1		T153	3		T143	1
valid_sources[0x28]	72	1		T42	1		T149	1		T154	1
valid_sources[0x29]	118	1		T31	22		T32	2		T33	2
valid_sources[0x2a]	106	1		T155	18		T34	1		T35	2
valid_sources[0x2b]	124	1		T146	4		T34	1		T35	3
valid_sources[0x2c]	72	1		T34	1		T35	4		T85	3
valid_sources[0x2d]	128	1		T147	1		T149	2		T36	1
valid_sources[0x2e]	83	1		T34	2		T31	3		T35	3
valid_sources[0x2f]	75	1		T156	7		T140	1		T34	2
valid_sources[0x30]	148	1		T75	1		T149	1		T34	1
valid_sources[0x31]	89	1		T34	1		T35	1		T32	2
valid_sources[0x32]	76	1		T157	1		T34	1		T31	7
valid_sources[0x33]	41	1		T36	1		T34	1		T35	3
valid_sources[0x34]	99	1		T27	1		T85	3		T92	1
valid_sources[0x35]	103	1		T51	1		T35	1		T32	2
valid_sources[0x36]	86	1		T144	1		T146	1		T35	4
valid_sources[0x37]	83	1		T42	1		T73	2		T147	1
valid_sources[0x38]	78	1		T73	2		T51	1		T122	2
valid_sources[0x39]	76	1		T34	1		T35	4		T81	1
valid_sources[0x3a]	266	1		T35	3		T32	1		T85	2
valid_sources[0x3b]	35	1		T34	1		T121	3		T158	3
valid_sources[0x3c]	93	1		T72	1		T73	6		T36	2
valid_sources[0x3d]	85	1		T70	5		T38	2		T35	4
valid_sources[0x3e]	54	1		T51	1		T34	2		T32	1
valid_sources[0x3f]	89	1		T35	3		T84	1		T91	1
valid_sources[0x40]	53	1		T35	7		T85	1		T92	2
valid_sources[0x41]	92	1		T35	3		T85	2		T92	1
valid_sources[0x42]	101	1		T151	1		T34	2		T35	5
valid_sources[0x43]	89	1		T36	2		T34	2		T35	2
valid_sources[0x44]	43	1		T34	1		T35	1		T32	1
valid_sources[0x45]	166	1		T152	2		T35	1		T32	1
valid_sources[0x46]	89	1		T72	1		T51	1		T140	1
valid_sources[0x47]	111	1		T36	3		T34	2		T35	2
valid_sources[0x48]	251	1		T26	1		T143	4		T35	1
valid_sources[0x49]	92	1		T149	1		T36	1		T34	1
valid_sources[0x4a]	76	1		T50	1		T34	2		T35	2
valid_sources[0x4b]	76	1		T34	1		T85	6		T92	2
valid_sources[0x4c]	69	1		T35	4		T85	3		T93	5
valid_sources[0x4d]	57	1		T34	1		T35	2		T85	3
valid_sources[0x4e]	73	1		T85	1		T93	1		T121	3
valid_sources[0x4f]	77	1		T35	2		T32	1		T81	2
valid_sources[0x50]	98	1		T34	5		T37	7		T35	2
valid_sources[0x51]	65	1		T159	1		T143	1		T34	2
valid_sources[0x52]	50	1		T42	1		T34	1		T35	5
valid_sources[0x53]	70	1		T154	1		T36	1		T34	2
valid_sources[0x54]	36	1		T34	2		T35	1		T33	3
valid_sources[0x55]	105	1		T34	2		T35	4		T32	8
valid_sources[0x56]	66	1		T36	1		T85	2		T92	1
valid_sources[0x57]	51	1		T72	1		T34	1		T35	1
valid_sources[0x58]	95	1		T34	2		T35	3		T85	5
valid_sources[0x59]	44	1		T147	1		T150	1		T34	2
valid_sources[0x5a]	79	1		T34	1		T35	5		T32	1
valid_sources[0x5b]	295	1		T140	1		T34	2		T81	1
valid_sources[0x5c]	55	1		T36	1		T34	1		T81	3
valid_sources[0x5d]	70	1		T34	2		T35	6		T81	1
valid_sources[0x5e]	87	1		T27	1		T119	3		T35	5
valid_sources[0x5f]	49	1		T34	1		T85	2		T93	3
valid_sources[0x60]	89	1		T35	1		T32	3		T84	8
valid_sources[0x61]	61	1		T51	1		T35	6		T32	1
valid_sources[0x62]	90	1		T147	2		T160	1		T35	5
valid_sources[0x63]	203	1		T49	1		T34	4		T35	1
valid_sources[0x64]	69	1		T27	1		T34	1		T35	2
valid_sources[0x65]	109	1		T139	1		T161	1		T34	3
valid_sources[0x66]	73	1		T34	1		T35	1		T32	2
valid_sources[0x67]	99	1		T75	1		T157	1		T152	1
valid_sources[0x68]	113	1		T27	1		T28	2		T147	1
valid_sources[0x69]	55	1		T26	1		T35	2		T85	3
valid_sources[0x6a]	61	1		T162	1		T85	1		T92	1
valid_sources[0x6b]	67	1		T38	6		T143	1		T35	3
valid_sources[0x6c]	143	1		T150	3		T34	2		T84	11
valid_sources[0x6d]	158	1		T149	1		T148	1		T34	1
valid_sources[0x6e]	171	1		T28	1		T149	1		T34	2
valid_sources[0x6f]	69	1		T72	1		T51	1		T34	2
valid_sources[0x70]	59	1		T28	1		T72	1		T36	1
valid_sources[0x71]	148	1		T147	1		T139	1		T35	3
valid_sources[0x72]	109	1		T37	20		T32	3		T85	2
valid_sources[0x73]	49	1		T119	2		T33	3		T81	1
valid_sources[0x74]	75	1		T34	1		T35	7		T80	2
valid_sources[0x75]	72	1		T34	1		T80	17		T85	1
valid_sources[0x76]	73	1		T35	3		T81	3		T85	2
valid_sources[0x77]	312	1		T154	1		T34	2		T85	4
valid_sources[0x78]	120	1		T36	2		T35	1		T85	4
valid_sources[0x79]	53	1		T35	3		T88	1		T85	1
valid_sources[0x7a]	93	1		T149	1		T34	1		T35	1
valid_sources[0x7b]	49	1		T34	2		T35	1		T81	1
valid_sources[0x7c]	93	1		T40	22		T34	5		T35	2
valid_sources[0x7d]	84	1		T154	1		T159	1		T143	1
valid_sources[0x7e]	94	1		T42	2		T38	2		T51	1
valid_sources[0x7f]	89	1		T149	1		T34	2		T35	4
valid_sources[0x80]	103	1		T65	1		T34	4		T32	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6598

1

T36

23

T34

69

T31

13

values[0x0]

all_enables

biggest_size

6298

1

T26

1

T27

3

T28

3

values[0x1]

all_enables

biggest_size

6123

1

T27

1

T71

2

T72

1