Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	233445	1		T2	119		T4	62		T6	10
full_word	526178	1		T2	100		T3	2		T4	11

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	759313	1		T2	219		T3	2		T4	73
auto[TlIntgErrCmd]	105	1		T31	4		T33	1		T82	6
auto[TlIntgErrData]	96	1		T31	4		T33	5		T82	3
auto[TlIntgErrBoth]	109	1		T31	2		T33	4		T82	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	481122	1		T2	97		T15	16		T8	42
auto[1]	278501	1		T2	122		T3	2		T4	73

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	195614	1		T2	43		T15	9		T8	15
auto[TlIntgErrNone]	partial	auto[1]	37550	1		T2	76		T4	62		T6	10
auto[TlIntgErrNone]	full_word	auto[0]	285368	1		T2	54		T15	7		T8	27
auto[TlIntgErrNone]	full_word	auto[1]	240781	1		T2	46		T3	2		T4	11
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T31	1		T82	2		T121	2
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T31	3		T33	1		T82	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T126	1		T127	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T124	1		T128	1		T127	1
auto[TlIntgErrData]	partial	auto[0]	43	1		T31	2		T33	2		T82	1
auto[TlIntgErrData]	partial	auto[1]	43	1		T31	2		T33	2		T82	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T33	1		T128	2		T129	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T130	1		T125	1		T131	2
auto[TlIntgErrBoth]	partial	auto[0]	42	1		T33	4		T82	4		T121	3
auto[TlIntgErrBoth]	partial	auto[1]	56	1		T31	2		T82	4		T121	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1		T82	2		T121	1		T132	2
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T82	1		T121	1		T125	1