Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.45	90.91	63.83	87.88		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	44613982	11045	0	0
late_debug_enable_rd_A	44613982	3478	0	0
late_debug_enable_regwen_rd_A	44613982	4199	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44613982	11045	0	0
T31	47854	2	0	0
T32	73768	58	0	0
T33	26125	2	0	0
T34	9501	262	0	0
T35	5961	580	0	0
T80	44595	196	0	0
T81	8940	30	0	0
T82	165086	4	0	0
T83	310771	26	0	0
T84	8532	416	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44613982	3478	0	0
T34	9501	74	0	0
T36	20493	21	0	0
T63	704361	28	0	0
T82	165086	76	0	0
T83	310771	47	0	0
T88	7690	12	0	0
T91	20434	22	0	0
T100	4641	6	0	0
T101	246478	155	0	0
T121	104677	78	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44613982	4199	0	0
T34	9501	75	0	0
T36	20493	5	0	0
T63	704361	39	0	0
T82	165086	71	0	0
T83	310771	67	0	0
T88	7690	3	0	0
T91	20434	22	0	0
T100	4641	1	0	0
T101	246478	102	0	0
T121	104677	99	0	0