Module Definition
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Module : prim_mubi8_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.45 90.91 63.83 87.88 57.14 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[7].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[7].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[7].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[7].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_mubi8_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 4 4


Assert Coverage for Module : prim_mubi8_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 166 166 0 0
OutputsKnown_A 20055373 20007505 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 20055373 20005342 0 498


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 166 166 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T16 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T30 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20055373 20007505 0 0
T1 284600 283684 0 0
T2 146435 145958 0 0
T3 1588 1534 0 0
T7 1963 1905 0 0
T10 96505 96441 0 0
T11 133785 133726 0 0
T16 5036 4971 0 0
T26 1670 1615 0 0
T27 1787 1737 0 0
T30 74241 74182 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20055373 20005342 0 498
T1 284600 283642 0 3
T2 146435 145937 0 3
T3 1588 1531 0 3
T7 1963 1902 0 3
T10 96505 96438 0 3
T11 133785 133723 0 3
T16 5036 4968 0 3
T26 1670 1612 0 3
T27 1787 1734 0 3
T30 74241 74179 0 3

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