Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	188792	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	569525	1		T1	12		T2	1		T6	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	456063	1		T4	16		T17	18		T18	6
values[0x0]	149010	1		T1	15		T2	2		T6	3
values[0x1]	153244	1		T1	30		T2	4		T6	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	145451	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	612866	1		T1	16		T2	2		T6	3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2693	1		T41	32		T36	10		T39	3
valid_sources[0x01]	3533	1		T63	1		T41	35		T36	17
valid_sources[0x02]	2619	1		T1	1		T59	1		T60	1
valid_sources[0x03]	2848	1		T18	4		T41	30		T39	1
valid_sources[0x04]	2380	1		T17	2		T41	26		T40	5
valid_sources[0x05]	3215	1		T41	27		T36	1		T39	1
valid_sources[0x06]	3057	1		T1	1		T59	1		T41	33
valid_sources[0x07]	3442	1		T22	1		T41	19		T39	1
valid_sources[0x08]	2765	1		T1	1		T41	38		T36	9
valid_sources[0x09]	2893	1		T17	1		T22	3		T41	37
valid_sources[0x0a]	2749	1		T76	1		T59	3		T60	2
valid_sources[0x0b]	2348	1		T17	1		T41	20		T36	10
valid_sources[0x0c]	2457	1		T22	1		T59	1		T41	11
valid_sources[0x0d]	2862	1		T113	1		T59	1		T41	24
valid_sources[0x0e]	3140	1		T60	1		T41	28		T36	2
valid_sources[0x0f]	2565	1		T41	16		T36	2		T39	1
valid_sources[0x10]	3353	1		T41	19		T39	2		T40	4
valid_sources[0x11]	2825	1		T59	1		T41	30		T36	17
valid_sources[0x12]	2844	1		T22	3		T60	3		T41	14
valid_sources[0x13]	2842	1		T7	2		T41	59		T36	4
valid_sources[0x14]	3175	1		T41	13		T40	2		T42	111
valid_sources[0x15]	2660	1		T7	1		T41	31		T40	4
valid_sources[0x16]	3173	1		T41	15		T39	1		T40	1
valid_sources[0x17]	2467	1		T23	1		T41	34		T36	11
valid_sources[0x18]	3537	1		T59	1		T60	2		T41	24
valid_sources[0x19]	2697	1		T59	1		T60	2		T41	31
valid_sources[0x1a]	2239	1		T41	24		T36	24		T39	1
valid_sources[0x1b]	2306	1		T41	23		T36	1		T40	1
valid_sources[0x1c]	2736	1		T17	1		T76	1		T59	1
valid_sources[0x1d]	2696	1		T60	1		T41	26		T36	1
valid_sources[0x1e]	2434	1		T22	1		T23	1		T41	16
valid_sources[0x1f]	2445	1		T60	1		T41	18		T36	2
valid_sources[0x20]	4517	1		T13	12		T22	2		T41	19
valid_sources[0x21]	3308	1		T41	24		T36	6		T39	2
valid_sources[0x22]	2502	1		T41	35		T40	4		T75	1
valid_sources[0x23]	2484	1		T23	1		T41	28		T36	11
valid_sources[0x24]	2494	1		T7	1		T59	1		T41	34
valid_sources[0x25]	2643	1		T41	26		T39	2		T40	1
valid_sources[0x26]	6695	1		T1	1		T22	2		T59	1
valid_sources[0x27]	2714	1		T1	1		T22	6		T59	2
valid_sources[0x28]	3055	1		T22	2		T23	1		T41	26
valid_sources[0x29]	3423	1		T5	1		T59	1		T60	1
valid_sources[0x2a]	3056	1		T2	1		T60	1		T41	22
valid_sources[0x2b]	2339	1		T59	2		T41	43		T36	2
valid_sources[0x2c]	2824	1		T76	1		T41	34		T36	5
valid_sources[0x2d]	2795	1		T41	34		T36	2		T40	3
valid_sources[0x2e]	3364	1		T60	1		T41	12		T36	21
valid_sources[0x2f]	2895	1		T76	1		T22	1		T59	1
valid_sources[0x30]	2907	1		T59	1		T41	26		T36	5
valid_sources[0x31]	10231	1		T41	18		T36	2		T39	2
valid_sources[0x32]	2428	1		T41	49		T36	15		T40	2
valid_sources[0x33]	2991	1		T17	1		T41	36		T36	1
valid_sources[0x34]	2537	1		T41	26		T36	3		T40	3
valid_sources[0x35]	2720	1		T1	1		T23	2		T60	3
valid_sources[0x36]	3529	1		T18	3		T41	35		T36	5
valid_sources[0x37]	2923	1		T22	1		T41	34		T36	13
valid_sources[0x38]	2515	1		T23	1		T41	20		T39	1
valid_sources[0x39]	2622	1		T1	1		T41	8		T36	5
valid_sources[0x3a]	2470	1		T41	23		T36	3		T39	1
valid_sources[0x3b]	2858	1		T7	1		T41	32		T39	4
valid_sources[0x3c]	2194	1		T41	26		T36	5		T39	1
valid_sources[0x3d]	2389	1		T76	1		T59	1		T41	18
valid_sources[0x3e]	2296	1		T41	32		T36	1		T39	1
valid_sources[0x3f]	2538	1		T60	2		T41	18		T36	23
valid_sources[0x40]	2658	1		T76	1		T41	27		T36	3
valid_sources[0x41]	3450	1		T1	2		T17	1		T60	1
valid_sources[0x42]	2777	1		T41	27		T36	5		T40	4
valid_sources[0x43]	2655	1		T1	1		T41	31		T36	19
valid_sources[0x44]	3785	1		T1	1		T41	28		T40	2
valid_sources[0x45]	2490	1		T1	1		T41	34		T36	4
valid_sources[0x46]	2277	1		T60	2		T41	18		T39	1
valid_sources[0x47]	2896	1		T41	22		T36	1		T39	2
valid_sources[0x48]	2978	1		T59	1		T41	21		T36	2
valid_sources[0x49]	3223	1		T41	35		T36	4		T40	6
valid_sources[0x4a]	3143	1		T60	1		T41	13		T39	1
valid_sources[0x4b]	1994	1		T60	3		T41	16		T36	4
valid_sources[0x4c]	2609	1		T17	1		T22	1		T59	1
valid_sources[0x4d]	2746	1		T41	15		T39	1		T40	7
valid_sources[0x4e]	4256	1		T1	1		T41	17		T36	7
valid_sources[0x4f]	2718	1		T17	1		T60	1		T41	15
valid_sources[0x50]	2993	1		T113	1		T41	18		T39	1
valid_sources[0x51]	3146	1		T41	13		T36	1		T39	1
valid_sources[0x52]	9817	1		T41	27		T36	4		T39	1
valid_sources[0x53]	2593	1		T41	26		T36	1		T40	2
valid_sources[0x54]	2942	1		T17	1		T59	1		T41	16
valid_sources[0x55]	2503	1		T6	8		T41	44		T36	1
valid_sources[0x56]	3022	1		T17	1		T60	1		T41	22
valid_sources[0x57]	3126	1		T22	1		T59	1		T41	16
valid_sources[0x58]	3215	1		T41	26		T36	35		T40	3
valid_sources[0x59]	4360	1		T17	1		T59	1		T41	40
valid_sources[0x5a]	2323	1		T59	2		T41	14		T36	5
valid_sources[0x5b]	2508	1		T41	39		T36	13		T39	2
valid_sources[0x5c]	2789	1		T1	1		T17	1		T60	1
valid_sources[0x5d]	2637	1		T22	1		T60	1		T41	23
valid_sources[0x5e]	2784	1		T41	21		T36	4		T39	3
valid_sources[0x5f]	3157	1		T41	27		T36	5		T39	2
valid_sources[0x60]	2608	1		T17	1		T59	1		T63	1
valid_sources[0x61]	2454	1		T22	2		T60	1		T41	14
valid_sources[0x62]	3201	1		T59	1		T41	20		T36	3
valid_sources[0x63]	2738	1		T2	1		T41	16		T36	12
valid_sources[0x64]	2842	1		T41	18		T39	1		T40	4
valid_sources[0x65]	2989	1		T32	29		T59	1		T41	16
valid_sources[0x66]	2367	1		T41	43		T39	1		T40	2
valid_sources[0x67]	2751	1		T60	1		T41	33		T39	2
valid_sources[0x68]	2654	1		T76	1		T41	17		T36	1
valid_sources[0x69]	2748	1		T1	1		T41	30		T39	1
valid_sources[0x6a]	2583	1		T17	1		T113	1		T59	1
valid_sources[0x6b]	3002	1		T41	26		T36	17		T39	1
valid_sources[0x6c]	3109	1		T7	1		T41	17		T39	1
valid_sources[0x6d]	3342	1		T41	23		T36	11		T40	1
valid_sources[0x6e]	2173	1		T17	1		T23	1		T61	49
valid_sources[0x6f]	3448	1		T18	5		T41	21		T36	8
valid_sources[0x70]	3077	1		T76	1		T41	15		T36	39
valid_sources[0x71]	3066	1		T41	34		T39	1		T40	3
valid_sources[0x72]	3133	1		T1	1		T17	1		T41	25
valid_sources[0x73]	3086	1		T59	1		T41	16		T36	2
valid_sources[0x74]	3785	1		T59	2		T60	1		T41	30
valid_sources[0x75]	2983	1		T1	1		T41	22		T36	2
valid_sources[0x76]	3401	1		T41	24		T36	11		T39	1
valid_sources[0x77]	2647	1		T1	2		T41	21		T36	46
valid_sources[0x78]	3368	1		T41	14		T36	3		T40	3
valid_sources[0x79]	2834	1		T17	2		T41	13		T40	1
valid_sources[0x7a]	3257	1		T1	1		T43	275		T41	30
valid_sources[0x7b]	2906	1		T59	1		T60	4		T41	24
valid_sources[0x7c]	3049	1		T60	2		T41	18		T36	4
valid_sources[0x7d]	3385	1		T41	23		T36	8		T39	2
valid_sources[0x7e]	2430	1		T59	1		T41	29		T36	3
valid_sources[0x7f]	2929	1		T41	12		T42	39		T75	9
valid_sources[0x80]	2939	1		T59	1		T41	7		T36	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

275424

1

T4

6

T17

9

T18

3

values[0x0]

all_enables

biggest_size

147181

1

T1

1

T2

1

T4

10

values[0x1]

all_enables

biggest_size

146920

1

T1

11

T6

2

T4

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4176	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	17767	1		T3	1		T29	1		T31	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7532	1		T43	3		T41	20		T36	71
values[0x0]	7136	1		T3	2		T29	6		T30	1
values[0x1]	7275	1		T3	5		T29	4		T30	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3159	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	18784	1		T3	1		T29	1		T31	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	92	1		T36	1		T77	7		T37	12
valid_sources[0x01]	139	1		T36	1		T42	1		T75	1
valid_sources[0x02]	66	1		T36	1		T75	4		T79	2
valid_sources[0x03]	50	1		T79	2		T132	4		T114	1
valid_sources[0x04]	75	1		T134	1		T36	1		T75	5
valid_sources[0x05]	71	1		T50	5		T135	1		T75	1
valid_sources[0x06]	55	1		T136	1		T137	3		T138	2
valid_sources[0x07]	99	1		T139	1		T140	1		T141	1
valid_sources[0x08]	92	1		T142	1		T36	1		T75	5
valid_sources[0x09]	64	1		T29	2		T75	1		T79	1
valid_sources[0x0a]	65	1		T89	2		T139	1		T78	1
valid_sources[0x0b]	142	1		T39	2		T75	1		T82	1
valid_sources[0x0c]	111	1		T41	3		T36	1		T75	2
valid_sources[0x0d]	92	1		T142	2		T36	3		T75	3
valid_sources[0x0e]	72	1		T36	2		T42	2		T75	3
valid_sources[0x0f]	55	1		T36	2		T39	1		T75	6
valid_sources[0x10]	96	1		T143	1		T36	1		T75	1
valid_sources[0x11]	64	1		T143	1		T36	2		T39	2
valid_sources[0x12]	81	1		T39	1		T42	1		T75	2
valid_sources[0x13]	86	1		T137	1		T144	1		T75	2
valid_sources[0x14]	61	1		T142	2		T36	2		T39	6
valid_sources[0x15]	72	1		T75	1		T87	1		T88	1
valid_sources[0x16]	55	1		T139	1		T135	1		T75	2
valid_sources[0x17]	75	1		T145	2		T36	1		T39	1
valid_sources[0x18]	103	1		T36	1		T39	13		T75	2
valid_sources[0x19]	48	1		T3	1		T146	2		T79	1
valid_sources[0x1a]	216	1		T40	150		T75	1		T78	2
valid_sources[0x1b]	77	1		T31	1		T54	1		T36	1
valid_sources[0x1c]	68	1		T39	2		T75	2		T91	1
valid_sources[0x1d]	72	1		T75	1		T37	10		T132	6
valid_sources[0x1e]	87	1		T36	3		T39	2		T42	1
valid_sources[0x1f]	76	1		T135	1		T36	1		T42	1
valid_sources[0x20]	70	1		T140	1		T138	1		T39	1
valid_sources[0x21]	70	1		T140	1		T75	1		T78	1
valid_sources[0x22]	93	1		T31	2		T44	1		T147	1
valid_sources[0x23]	93	1		T147	1		T148	1		T142	1
valid_sources[0x24]	67	1		T36	3		T42	1		T75	3
valid_sources[0x25]	229	1		T89	1		T75	3		T37	7
valid_sources[0x26]	76	1		T139	1		T36	1		T78	1
valid_sources[0x27]	108	1		T41	18		T79	3		T91	3
valid_sources[0x28]	64	1		T36	1		T39	1		T75	2
valid_sources[0x29]	66	1		T36	5		T75	5		T80	4
valid_sources[0x2a]	73	1		T36	2		T75	2		T79	3
valid_sources[0x2b]	74	1		T143	1		T36	2		T78	1
valid_sources[0x2c]	53	1		T44	1		T139	1		T75	4
valid_sources[0x2d]	143	1		T80	2		T87	2		T91	1
valid_sources[0x2e]	67	1		T36	1		T79	1		T86	1
valid_sources[0x2f]	72	1		T148	4		T141	2		T75	3
valid_sources[0x30]	127	1		T36	1		T39	1		T75	3
valid_sources[0x31]	78	1		T89	1		T80	2		T132	4
valid_sources[0x32]	72	1		T36	1		T75	2		T78	1
valid_sources[0x33]	60	1		T149	2		T134	1		T39	2
valid_sources[0x34]	62	1		T36	1		T42	1		T75	2
valid_sources[0x35]	86	1		T143	1		T36	2		T39	5
valid_sources[0x36]	147	1		T36	2		T75	1		T88	1
valid_sources[0x37]	84	1		T150	3		T39	6		T75	1
valid_sources[0x38]	111	1		T136	1		T146	5		T41	2
valid_sources[0x39]	91	1		T135	1		T39	3		T75	1
valid_sources[0x3a]	58	1		T36	1		T39	2		T75	1
valid_sources[0x3b]	54	1		T75	1		T80	3		T91	1
valid_sources[0x3c]	85	1		T151	1		T36	1		T75	5
valid_sources[0x3d]	52	1		T75	3		T78	2		T79	4
valid_sources[0x3e]	65	1		T152	1		T42	1		T75	4
valid_sources[0x3f]	99	1		T39	11		T42	1		T75	1
valid_sources[0x40]	83	1		T41	5		T36	5		T75	5
valid_sources[0x41]	73	1		T139	1		T142	1		T36	2
valid_sources[0x42]	102	1		T36	4		T75	2		T78	1
valid_sources[0x43]	86	1		T143	1		T36	1		T75	1
valid_sources[0x44]	66	1		T89	1		T143	1		T75	3
valid_sources[0x45]	79	1		T139	1		T75	5		T79	4
valid_sources[0x46]	112	1		T146	3		T36	1		T42	2
valid_sources[0x47]	156	1		T136	1		T39	5		T75	5
valid_sources[0x48]	113	1		T148	3		T75	1		T78	4
valid_sources[0x49]	75	1		T36	2		T75	3		T82	1
valid_sources[0x4a]	65	1		T44	4		T42	2		T75	1
valid_sources[0x4b]	58	1		T143	1		T142	1		T75	1
valid_sources[0x4c]	300	1		T49	1		T39	6		T42	1
valid_sources[0x4d]	75	1		T44	1		T75	4		T82	1
valid_sources[0x4e]	73	1		T153	10		T36	2		T75	1
valid_sources[0x4f]	61	1		T154	3		T36	1		T39	1
valid_sources[0x50]	55	1		T36	2		T75	1		T78	1
valid_sources[0x51]	83	1		T147	1		T36	1		T78	4
valid_sources[0x52]	39	1		T75	1		T79	1		T85	1
valid_sources[0x53]	92	1		T36	2		T75	5		T79	2
valid_sources[0x54]	75	1		T75	3		T83	1		T79	3
valid_sources[0x55]	58	1		T36	1		T75	1		T78	1
valid_sources[0x56]	166	1		T39	10		T40	91		T75	3
valid_sources[0x57]	78	1		T143	1		T36	1		T42	1
valid_sources[0x58]	84	1		T75	3		T79	2		T88	3
valid_sources[0x59]	67	1		T54	2		T36	3		T39	1
valid_sources[0x5a]	146	1		T36	1		T77	98		T91	1
valid_sources[0x5b]	61	1		T42	1		T75	3		T79	1
valid_sources[0x5c]	112	1		T44	1		T75	8		T82	1
valid_sources[0x5d]	77	1		T54	1		T155	5		T75	5
valid_sources[0x5e]	86	1		T39	1		T75	1		T78	2
valid_sources[0x5f]	96	1		T147	1		T134	1		T138	1
valid_sources[0x60]	56	1		T139	1		T36	1		T39	1
valid_sources[0x61]	82	1		T29	1		T143	1		T36	2
valid_sources[0x62]	105	1		T44	1		T138	1		T39	5
valid_sources[0x63]	145	1		T156	6		T140	3		T41	2
valid_sources[0x64]	105	1		T142	1		T75	5		T84	4
valid_sources[0x65]	61	1		T31	1		T142	1		T75	2
valid_sources[0x66]	62	1		T138	1		T135	1		T36	1
valid_sources[0x67]	64	1		T44	1		T36	2		T75	4
valid_sources[0x68]	106	1		T36	1		T75	6		T79	4
valid_sources[0x69]	75	1		T44	1		T56	1		T39	1
valid_sources[0x6a]	57	1		T147	1		T39	1		T132	3
valid_sources[0x6b]	56	1		T39	9		T75	2		T83	4
valid_sources[0x6c]	64	1		T147	1		T138	1		T36	4
valid_sources[0x6d]	89	1		T36	1		T42	2		T75	1
valid_sources[0x6e]	64	1		T136	3		T134	1		T36	3
valid_sources[0x6f]	70	1		T36	2		T75	1		T37	13
valid_sources[0x70]	136	1		T157	11		T75	5		T83	2
valid_sources[0x71]	131	1		T36	1		T42	1		T75	1
valid_sources[0x72]	78	1		T30	1		T139	1		T36	1
valid_sources[0x73]	72	1		T36	1		T87	1		T81	4
valid_sources[0x74]	82	1		T36	1		T39	1		T75	1
valid_sources[0x75]	84	1		T29	1		T36	2		T39	1
valid_sources[0x76]	54	1		T143	1		T75	2		T85	1
valid_sources[0x77]	60	1		T142	1		T75	4		T82	1
valid_sources[0x78]	114	1		T39	4		T42	1		T75	2
valid_sources[0x79]	80	1		T36	1		T39	1		T75	3
valid_sources[0x7a]	81	1		T39	3		T42	1		T75	2
valid_sources[0x7b]	111	1		T36	1		T39	17		T75	2
valid_sources[0x7c]	63	1		T36	2		T39	1		T75	1
valid_sources[0x7d]	53	1		T36	4		T75	2		T88	1
valid_sources[0x7e]	74	1		T144	1		T75	3		T37	12
valid_sources[0x7f]	37	1		T44	1		T36	1		T75	1
valid_sources[0x80]	61	1		T94	15		T72	1		T132	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5464

1

T43

2

T41

20

T36

65

values[0x0]

all_enables

biggest_size

6310

1

T29

1

T31

1

T47

2

values[0x1]

all_enables

biggest_size

5993

1

T3

1

T47

2

T35

1