Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	222899	1		T1	33		T2	5		T6	6
full_word	570853	1		T1	12		T2	1		T6	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	793422	1		T1	45		T2	6		T6	8
auto[TlIntgErrCmd]	128	1		T81	4		T116	3		T117	6
auto[TlIntgErrData]	106	1		T81	3		T116	4		T117	2
auto[TlIntgErrBoth]	96	1		T81	3		T116	3		T117	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	457671	1		T4	16		T17	18		T18	6
auto[1]	336081	1		T1	45		T2	6		T6	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	181964	1		T4	10		T17	9		T18	3
auto[TlIntgErrNone]	partial	auto[1]	40636	1		T1	33		T2	5		T6	6
auto[TlIntgErrNone]	full_word	auto[0]	275566	1		T4	6		T17	9		T18	3
auto[TlIntgErrNone]	full_word	auto[1]	295256	1		T1	12		T2	1		T6	2
auto[TlIntgErrCmd]	partial	auto[0]	48	1		T81	1		T116	1		T117	2
auto[TlIntgErrCmd]	partial	auto[1]	69	1		T81	2		T116	1		T117	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T81	1		T127	1		T126	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T116	1		T120	2		T121	1
auto[TlIntgErrData]	partial	auto[0]	47	1		T81	2		T116	2		T121	4
auto[TlIntgErrData]	partial	auto[1]	49	1		T81	1		T116	1		T117	2
auto[TlIntgErrData]	full_word	auto[0]	2	1		T128	1		T129	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	8	1		T116	1		T121	1		T123	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1		T81	1		T116	2		T120	7
auto[TlIntgErrBoth]	partial	auto[1]	49	1		T81	2		T116	1		T117	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T120	1		T130	1		T124	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T121	1		T125	1		T127	1