Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.45	90.91	63.83	87.88		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	51849467	12204	0	0
late_debug_enable_rd_A	51849467	2118	0	0
late_debug_enable_regwen_rd_A	51849467	2160	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51849467	12204	0	0
T36	187302	73	0	0
T37	66592	52	0	0
T38	222116	9	0	0
T39	11957	556	0	0
T40	25595	595	0	0
T75	23892	537	0	0
T77	9720	87	0	0
T78	2956	138	0	0
T79	11804	266	0	0
T80	58337	20	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51849467	2118	0	0
T37	66592	29	0	0
T39	11957	89	0	0
T41	39954	35	0	0
T43	4443	3	0	0
T80	58337	25	0	0
T84	9667	17	0	0
T88	45403	17	0	0
T94	55315	62	0	0
T95	7875	10	0	0
T114	83839	47	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51849467	2160	0	0
T37	66592	90	0	0
T39	11957	68	0	0
T41	39954	22	0	0
T43	4443	6	0	0
T80	58337	40	0	0
T84	9667	1	0	0
T88	45403	53	0	0
T94	55315	32	0	0
T95	7875	16	0	0
T114	83839	34	0	0