SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.45 | 90.91 | 63.83 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.45 | 90.91 | 63.83 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.45 | 90.91 | 63.83 | 87.88 | 57.14 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.45 | 90.91 | 63.83 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
81.44 | 96.08 | 77.78 | 100.00 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 990 | 990 | 0 | 0 |
OutputsKnown_A | 169663098 | 169402200 | 0 | 0 |
gen_flops.OutputDelay_A | 84831549 | 84695268 | 0 | 1485 |
gen_no_flops.OutputDelay_A | 84831549 | 84701100 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 990 | 990 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T6 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T10 | 6 | 6 | 0 | 0 |
T16 | 6 | 6 | 0 | 0 |
T29 | 6 | 6 | 0 | 0 |
T30 | 6 | 6 | 0 | 0 |
T31 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 169663098 | 169402200 | 0 | 0 |
T1 | 785256 | 784626 | 0 | 0 |
T2 | 136896 | 136476 | 0 | 0 |
T3 | 6810 | 6432 | 0 | 0 |
T6 | 62982 | 62682 | 0 | 0 |
T7 | 67920 | 67464 | 0 | 0 |
T10 | 1977570 | 1973970 | 0 | 0 |
T16 | 20052 | 19704 | 0 | 0 |
T29 | 12324 | 12012 | 0 | 0 |
T30 | 7254 | 6930 | 0 | 0 |
T31 | 11328 | 10926 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 84831549 | 84695268 | 0 | 1485 |
T1 | 392628 | 392295 | 0 | 9 |
T2 | 68448 | 68229 | 0 | 9 |
T3 | 3405 | 3207 | 0 | 9 |
T6 | 31491 | 31332 | 0 | 9 |
T7 | 33960 | 33723 | 0 | 9 |
T10 | 988785 | 986895 | 0 | 9 |
T16 | 10026 | 9843 | 0 | 9 |
T29 | 6162 | 5997 | 0 | 9 |
T30 | 3627 | 3456 | 0 | 9 |
T31 | 5664 | 5454 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 84831549 | 84701100 | 0 | 0 |
T1 | 392628 | 392313 | 0 | 0 |
T2 | 68448 | 68238 | 0 | 0 |
T3 | 3405 | 3216 | 0 | 0 |
T6 | 31491 | 31341 | 0 | 0 |
T7 | 33960 | 33732 | 0 | 0 |
T10 | 988785 | 986985 | 0 | 0 |
T16 | 10026 | 9852 | 0 | 0 |
T29 | 6162 | 6006 | 0 | 0 |
T30 | 3627 | 3465 | 0 | 0 |
T31 | 5664 | 5463 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 165 | 165 | 0 | 0 |
OutputsKnown_A | 28277183 | 28233700 | 0 | 0 |
gen_flops.OutputDelay_A | 28277183 | 28231756 | 0 | 495 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 165 | 165 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 28277183 | 28233700 | 0 | 0 |
T1 | 130876 | 130771 | 0 | 0 |
T2 | 22816 | 22746 | 0 | 0 |
T3 | 1135 | 1072 | 0 | 0 |
T6 | 10497 | 10447 | 0 | 0 |
T7 | 11320 | 11244 | 0 | 0 |
T10 | 329595 | 328995 | 0 | 0 |
T16 | 3342 | 3284 | 0 | 0 |
T29 | 2054 | 2002 | 0 | 0 |
T30 | 1209 | 1155 | 0 | 0 |
T31 | 1888 | 1821 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 28277183 | 28231756 | 0 | 495 |
T1 | 130876 | 130765 | 0 | 3 |
T2 | 22816 | 22743 | 0 | 3 |
T3 | 1135 | 1069 | 0 | 3 |
T6 | 10497 | 10444 | 0 | 3 |
T7 | 11320 | 11241 | 0 | 3 |
T10 | 329595 | 328965 | 0 | 3 |
T16 | 3342 | 3281 | 0 | 3 |
T29 | 2054 | 1999 | 0 | 3 |
T30 | 1209 | 1152 | 0 | 3 |
T31 | 1888 | 1818 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 165 | 165 | 0 | 0 |
OutputsKnown_A | 28277183 | 28233700 | 0 | 0 |
gen_flops.OutputDelay_A | 28277183 | 28231756 | 0 | 495 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 165 | 165 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 28277183 | 28233700 | 0 | 0 |
T1 | 130876 | 130771 | 0 | 0 |
T2 | 22816 | 22746 | 0 | 0 |
T3 | 1135 | 1072 | 0 | 0 |
T6 | 10497 | 10447 | 0 | 0 |
T7 | 11320 | 11244 | 0 | 0 |
T10 | 329595 | 328995 | 0 | 0 |
T16 | 3342 | 3284 | 0 | 0 |
T29 | 2054 | 2002 | 0 | 0 |
T30 | 1209 | 1155 | 0 | 0 |
T31 | 1888 | 1821 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 28277183 | 28231756 | 0 | 495 |
T1 | 130876 | 130765 | 0 | 3 |
T2 | 22816 | 22743 | 0 | 3 |
T3 | 1135 | 1069 | 0 | 3 |
T6 | 10497 | 10444 | 0 | 3 |
T7 | 11320 | 11241 | 0 | 3 |
T10 | 329595 | 328965 | 0 | 3 |
T16 | 3342 | 3281 | 0 | 3 |
T29 | 2054 | 1999 | 0 | 3 |
T30 | 1209 | 1152 | 0 | 3 |
T31 | 1888 | 1818 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 165 | 165 | 0 | 0 |
OutputsKnown_A | 28277183 | 28233700 | 0 | 0 |
gen_no_flops.OutputDelay_A | 28277183 | 28233700 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 165 | 165 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 28277183 | 28233700 | 0 | 0 |
T1 | 130876 | 130771 | 0 | 0 |
T2 | 22816 | 22746 | 0 | 0 |
T3 | 1135 | 1072 | 0 | 0 |
T6 | 10497 | 10447 | 0 | 0 |
T7 | 11320 | 11244 | 0 | 0 |
T10 | 329595 | 328995 | 0 | 0 |
T16 | 3342 | 3284 | 0 | 0 |
T29 | 2054 | 2002 | 0 | 0 |
T30 | 1209 | 1155 | 0 | 0 |
T31 | 1888 | 1821 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 28277183 | 28233700 | 0 | 0 |
T1 | 130876 | 130771 | 0 | 0 |
T2 | 22816 | 22746 | 0 | 0 |
T3 | 1135 | 1072 | 0 | 0 |
T6 | 10497 | 10447 | 0 | 0 |
T7 | 11320 | 11244 | 0 | 0 |
T10 | 329595 | 328995 | 0 | 0 |
T16 | 3342 | 3284 | 0 | 0 |
T29 | 2054 | 2002 | 0 | 0 |
T30 | 1209 | 1155 | 0 | 0 |
T31 | 1888 | 1821 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 165 | 165 | 0 | 0 |
OutputsKnown_A | 28277183 | 28233700 | 0 | 0 |
gen_flops.OutputDelay_A | 28277183 | 28231756 | 0 | 495 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 165 | 165 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 28277183 | 28233700 | 0 | 0 |
T1 | 130876 | 130771 | 0 | 0 |
T2 | 22816 | 22746 | 0 | 0 |
T3 | 1135 | 1072 | 0 | 0 |
T6 | 10497 | 10447 | 0 | 0 |
T7 | 11320 | 11244 | 0 | 0 |
T10 | 329595 | 328995 | 0 | 0 |
T16 | 3342 | 3284 | 0 | 0 |
T29 | 2054 | 2002 | 0 | 0 |
T30 | 1209 | 1155 | 0 | 0 |
T31 | 1888 | 1821 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 28277183 | 28231756 | 0 | 495 |
T1 | 130876 | 130765 | 0 | 3 |
T2 | 22816 | 22743 | 0 | 3 |
T3 | 1135 | 1069 | 0 | 3 |
T6 | 10497 | 10444 | 0 | 3 |
T7 | 11320 | 11241 | 0 | 3 |
T10 | 329595 | 328965 | 0 | 3 |
T16 | 3342 | 3281 | 0 | 3 |
T29 | 2054 | 1999 | 0 | 3 |
T30 | 1209 | 1152 | 0 | 3 |
T31 | 1888 | 1818 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 165 | 165 | 0 | 0 |
OutputsKnown_A | 28277183 | 28233700 | 0 | 0 |
gen_no_flops.OutputDelay_A | 28277183 | 28233700 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 165 | 165 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 28277183 | 28233700 | 0 | 0 |
T1 | 130876 | 130771 | 0 | 0 |
T2 | 22816 | 22746 | 0 | 0 |
T3 | 1135 | 1072 | 0 | 0 |
T6 | 10497 | 10447 | 0 | 0 |
T7 | 11320 | 11244 | 0 | 0 |
T10 | 329595 | 328995 | 0 | 0 |
T16 | 3342 | 3284 | 0 | 0 |
T29 | 2054 | 2002 | 0 | 0 |
T30 | 1209 | 1155 | 0 | 0 |
T31 | 1888 | 1821 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 28277183 | 28233700 | 0 | 0 |
T1 | 130876 | 130771 | 0 | 0 |
T2 | 22816 | 22746 | 0 | 0 |
T3 | 1135 | 1072 | 0 | 0 |
T6 | 10497 | 10447 | 0 | 0 |
T7 | 11320 | 11244 | 0 | 0 |
T10 | 329595 | 328995 | 0 | 0 |
T16 | 3342 | 3284 | 0 | 0 |
T29 | 2054 | 2002 | 0 | 0 |
T30 | 1209 | 1155 | 0 | 0 |
T31 | 1888 | 1821 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 165 | 165 | 0 | 0 |
OutputsKnown_A | 28277183 | 28233700 | 0 | 0 |
gen_no_flops.OutputDelay_A | 28277183 | 28233700 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 165 | 165 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 28277183 | 28233700 | 0 | 0 |
T1 | 130876 | 130771 | 0 | 0 |
T2 | 22816 | 22746 | 0 | 0 |
T3 | 1135 | 1072 | 0 | 0 |
T6 | 10497 | 10447 | 0 | 0 |
T7 | 11320 | 11244 | 0 | 0 |
T10 | 329595 | 328995 | 0 | 0 |
T16 | 3342 | 3284 | 0 | 0 |
T29 | 2054 | 2002 | 0 | 0 |
T30 | 1209 | 1155 | 0 | 0 |
T31 | 1888 | 1821 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 28277183 | 28233700 | 0 | 0 |
T1 | 130876 | 130771 | 0 | 0 |
T2 | 22816 | 22746 | 0 | 0 |
T3 | 1135 | 1072 | 0 | 0 |
T6 | 10497 | 10447 | 0 | 0 |
T7 | 11320 | 11244 | 0 | 0 |
T10 | 329595 | 328995 | 0 | 0 |
T16 | 3342 | 3284 | 0 | 0 |
T29 | 2054 | 2002 | 0 | 0 |
T30 | 1209 | 1155 | 0 | 0 |
T31 | 1888 | 1821 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |