Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 179734 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 528618 1 T1 18 T6 2 T4 40



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 443796 1 T4 24 T15 8 T16 4
values[0x0] 129897 1 T1 58 T2 1 T4 46
values[0x1] 134659 1 T1 45 T6 2 T4 41



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 136544 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 571808 1 T1 28 T6 2 T4 50



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3077 1 T17 1 T58 1 T5 2
valid_sources[0x01] 2325 1 T17 1 T142 2 T36 8
valid_sources[0x02] 2693 1 T1 103 T143 1 T7 1
valid_sources[0x03] 6684 1 T15 5 T7 1 T144 1
valid_sources[0x04] 2395 1 T143 1 T144 1 T145 1
valid_sources[0x05] 2525 1 T2 1 T142 3 T144 2
valid_sources[0x06] 3489 1 T142 1 T54 1 T36 6
valid_sources[0x07] 2634 1 T20 2 T7 1 T142 3
valid_sources[0x08] 2556 1 T143 1 T146 1 T142 1
valid_sources[0x09] 2771 1 T17 1 T5 3 T36 4
valid_sources[0x0a] 3078 1 T53 1 T144 1 T145 1
valid_sources[0x0b] 3268 1 T53 1 T56 5 T145 2
valid_sources[0x0c] 2952 1 T41 2 T147 1 T29 1
valid_sources[0x0d] 2397 1 T53 1 T36 1 T37 10
valid_sources[0x0e] 3511 1 T7 1 T142 2 T36 3
valid_sources[0x0f] 3105 1 T17 1 T5 1 T144 1
valid_sources[0x10] 2720 1 T17 2 T5 4 T56 4
valid_sources[0x11] 2577 1 T7 1 T147 1 T144 1
valid_sources[0x12] 2264 1 T17 2 T53 2 T142 2
valid_sources[0x13] 2643 1 T55 42 T54 2 T36 5
valid_sources[0x14] 2565 1 T41 1 T54 1 T36 1
valid_sources[0x15] 2535 1 T6 2 T142 2 T36 2
valid_sources[0x16] 2488 1 T17 1 T56 3 T142 1
valid_sources[0x17] 5232 1 T142 2 T34 2 T37 34
valid_sources[0x18] 2151 1 T15 7 T7 1 T142 1
valid_sources[0x19] 2749 1 T29 1 T144 1 T36 1
valid_sources[0x1a] 2485 1 T17 1 T29 2 T34 1
valid_sources[0x1b] 3810 1 T146 1 T147 1 T29 1
valid_sources[0x1c] 2470 1 T17 1 T41 1 T29 4
valid_sources[0x1d] 2675 1 T17 2 T20 6 T143 1
valid_sources[0x1e] 3023 1 T5 1 T56 2 T29 6
valid_sources[0x1f] 2296 1 T34 1 T37 7 T31 9
valid_sources[0x20] 2597 1 T143 2 T147 1 T54 1
valid_sources[0x21] 2199 1 T4 17 T36 4 T34 1
valid_sources[0x22] 2527 1 T15 1 T146 1 T53 3
valid_sources[0x23] 3009 1 T146 1 T7 1 T36 4
valid_sources[0x24] 3022 1 T17 1 T7 1 T56 3
valid_sources[0x25] 2719 1 T17 1 T142 2 T144 1
valid_sources[0x26] 2714 1 T7 1 T53 1 T54 2
valid_sources[0x27] 2381 1 T17 1 T56 2 T29 4
valid_sources[0x28] 3399 1 T147 1 T36 3 T34 1
valid_sources[0x29] 2646 1 T17 1 T7 1 T145 1
valid_sources[0x2a] 3010 1 T17 1 T147 1 T142 1
valid_sources[0x2b] 2702 1 T36 1 T34 2 T37 16
valid_sources[0x2c] 2806 1 T7 1 T53 2 T54 1
valid_sources[0x2d] 2407 1 T144 2 T36 2 T34 2
valid_sources[0x2e] 2615 1 T17 1 T53 1 T36 5
valid_sources[0x2f] 2832 1 T41 13 T144 1 T36 4
valid_sources[0x30] 2819 1 T15 8 T11 12 T142 1
valid_sources[0x31] 3369 1 T4 1 T5 2 T148 1
valid_sources[0x32] 2445 1 T17 1 T144 1 T54 1
valid_sources[0x33] 2413 1 T147 1 T56 2 T144 1
valid_sources[0x34] 2762 1 T7 1 T37 16 T31 30
valid_sources[0x35] 2709 1 T17 1 T147 1 T56 6
valid_sources[0x36] 2568 1 T41 4 T143 1 T144 1
valid_sources[0x37] 2442 1 T20 5 T147 1 T142 2
valid_sources[0x38] 2952 1 T17 2 T36 1 T34 4
valid_sources[0x39] 2127 1 T142 1 T36 6 T34 1
valid_sources[0x3a] 2646 1 T14 6 T17 1 T149 1
valid_sources[0x3b] 2286 1 T41 7 T20 2 T29 13
valid_sources[0x3c] 2621 1 T5 1 T149 1 T36 1
valid_sources[0x3d] 4011 1 T53 1 T54 2 T145 1
valid_sources[0x3e] 2601 1 T15 2 T145 1 T36 1
valid_sources[0x3f] 2707 1 T17 1 T144 1 T36 1
valid_sources[0x40] 2435 1 T17 1 T36 3 T34 1
valid_sources[0x41] 2554 1 T4 10 T17 1 T53 1
valid_sources[0x42] 2373 1 T53 1 T36 2 T37 7
valid_sources[0x43] 2438 1 T5 3 T150 3 T54 1
valid_sources[0x44] 2362 1 T41 1 T20 1 T143 1
valid_sources[0x45] 2766 1 T146 1 T7 1 T57 1
valid_sources[0x46] 2294 1 T53 1 T147 1 T57 8
valid_sources[0x47] 2771 1 T53 1 T37 11 T31 20
valid_sources[0x48] 2656 1 T17 1 T144 1 T37 40
valid_sources[0x49] 2521 1 T17 1 T53 3 T145 2
valid_sources[0x4a] 2590 1 T17 1 T56 1 T144 1
valid_sources[0x4b] 2687 1 T143 1 T53 4 T46 1
valid_sources[0x4c] 2873 1 T142 3 T144 2 T36 2
valid_sources[0x4d] 2342 1 T147 1 T36 2 T37 13
valid_sources[0x4e] 3027 1 T143 1 T56 1 T142 1
valid_sources[0x4f] 2471 1 T17 1 T5 4 T142 1
valid_sources[0x50] 2583 1 T144 2 T36 5 T37 19
valid_sources[0x51] 2784 1 T143 1 T53 1 T150 3
valid_sources[0x52] 3299 1 T143 2 T142 3 T34 3
valid_sources[0x53] 5208 1 T7 1 T56 1 T142 1
valid_sources[0x54] 3106 1 T41 6 T7 1 T54 1
valid_sources[0x55] 2479 1 T41 2 T146 1 T147 1
valid_sources[0x56] 2268 1 T29 3 T144 1 T37 50
valid_sources[0x57] 2686 1 T54 1 T36 3 T34 1
valid_sources[0x58] 2302 1 T4 10 T17 1 T7 2
valid_sources[0x59] 3042 1 T147 1 T54 1 T36 2
valid_sources[0x5a] 7366 1 T17 1 T142 1 T148 1
valid_sources[0x5b] 2542 1 T53 1 T56 2 T144 1
valid_sources[0x5c] 3028 1 T75 20 T36 2 T34 2
valid_sources[0x5d] 3666 1 T145 1 T36 2 T34 2
valid_sources[0x5e] 2363 1 T142 1 T37 42 T31 38
valid_sources[0x5f] 2785 1 T41 1 T143 2 T142 6
valid_sources[0x60] 3005 1 T41 1 T144 1 T54 1
valid_sources[0x61] 2588 1 T17 1 T5 1 T29 1
valid_sources[0x62] 2463 1 T7 1 T36 1 T34 1
valid_sources[0x63] 2598 1 T143 1 T53 1 T144 3
valid_sources[0x64] 2659 1 T142 2 T36 3 T34 2
valid_sources[0x65] 2610 1 T17 1 T46 1 T144 1
valid_sources[0x66] 2906 1 T20 5 T142 2 T36 1
valid_sources[0x67] 2576 1 T17 1 T53 1 T142 1
valid_sources[0x68] 2332 1 T46 1 T145 1 T36 3
valid_sources[0x69] 2717 1 T54 1 T36 1 T34 2
valid_sources[0x6a] 2764 1 T54 1 T36 2 T37 15
valid_sources[0x6b] 2422 1 T58 1 T5 3 T53 1
valid_sources[0x6c] 2675 1 T5 1 T144 1 T36 3
valid_sources[0x6d] 3225 1 T17 1 T143 1 T144 4
valid_sources[0x6e] 2275 1 T143 1 T147 1 T36 3
valid_sources[0x6f] 2558 1 T7 1 T144 1 T145 4
valid_sources[0x70] 2951 1 T5 3 T46 2 T142 1
valid_sources[0x71] 2412 1 T17 1 T53 1 T147 1
valid_sources[0x72] 2570 1 T5 2 T150 5 T145 3
valid_sources[0x73] 2394 1 T17 1 T58 1 T54 2
valid_sources[0x74] 2981 1 T17 1 T147 1 T142 1
valid_sources[0x75] 2615 1 T58 2 T36 8 T34 3
valid_sources[0x76] 2507 1 T146 1 T144 2 T36 6
valid_sources[0x77] 2362 1 T17 1 T5 6 T7 2
valid_sources[0x78] 2776 1 T54 3 T36 1 T34 1
valid_sources[0x79] 6847 1 T7 1 T36 2 T35 1
valid_sources[0x7a] 2854 1 T5 5 T144 1 T36 1
valid_sources[0x7b] 3125 1 T17 1 T20 4 T143 1
valid_sources[0x7c] 2784 1 T5 1 T147 1 T36 4
valid_sources[0x7d] 2762 1 T56 4 T145 1 T37 85
valid_sources[0x7e] 2842 1 T142 2 T36 4 T37 21
valid_sources[0x7f] 2620 1 T7 2 T53 2 T29 5
valid_sources[0x80] 2904 1 T36 1 T34 1 T37 9



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 272872 1 T4 13 T15 3 T16 3
values[0x0] all_enables biggest_size 128012 1 T1 13 T4 17 T14 2
values[0x1] all_enables biggest_size 127734 1 T1 5 T6 2 T4 10


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4696 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 19823 1 T24 3 T25 1 T26 3



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 9692 1 T36 3 T34 34 T35 28
values[0x0] 7306 1 T24 9 T25 4 T26 4
values[0x1] 7521 1 T24 8 T25 2 T26 5



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3589 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 20930 1 T24 3 T25 3 T26 4



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 82 1 T151 1 T35 1 T71 1
valid_sources[0x01] 67 1 T31 1 T61 2 T84 3
valid_sources[0x02] 92 1 T152 1 T31 1 T61 1
valid_sources[0x03] 72 1 T153 7 T76 1 T125 1
valid_sources[0x04] 53 1 T141 1 T154 2 T128 9
valid_sources[0x05] 95 1 T38 2 T67 1 T151 1
valid_sources[0x06] 51 1 T155 12 T125 1 T118 1
valid_sources[0x07] 237 1 T35 1 T76 1 T33 3
valid_sources[0x08] 92 1 T35 1 T61 2 T125 1
valid_sources[0x09] 133 1 T156 1 T157 2 T158 1
valid_sources[0x0a] 83 1 T159 1 T35 3 T76 7
valid_sources[0x0b] 66 1 T152 1 T76 1 T125 1
valid_sources[0x0c] 53 1 T158 1 T76 4 T77 2
valid_sources[0x0d] 62 1 T160 2 T161 1 T34 1
valid_sources[0x0e] 143 1 T76 1 T32 4 T80 24
valid_sources[0x0f] 78 1 T76 7 T71 1 T141 4
valid_sources[0x10] 97 1 T162 1 T163 1 T35 1
valid_sources[0x11] 70 1 T35 1 T125 2 T141 1
valid_sources[0x12] 136 1 T164 1 T35 2 T31 1
valid_sources[0x13] 96 1 T68 1 T35 1 T31 3
valid_sources[0x14] 72 1 T165 1 T35 3 T84 3
valid_sources[0x15] 278 1 T35 2 T31 9 T76 1
valid_sources[0x16] 73 1 T39 1 T32 1 T125 1
valid_sources[0x17] 66 1 T155 4 T166 9 T31 1
valid_sources[0x18] 47 1 T31 2 T77 1 T61 1
valid_sources[0x19] 76 1 T68 1 T158 1 T37 21
valid_sources[0x1a] 61 1 T68 1 T162 1 T159 1
valid_sources[0x1b] 81 1 T68 1 T35 1 T81 3
valid_sources[0x1c] 84 1 T79 3 T125 4 T141 2
valid_sources[0x1d] 76 1 T163 3 T125 2 T154 3
valid_sources[0x1e] 72 1 T125 3 T141 2 T154 3
valid_sources[0x1f] 48 1 T35 1 T32 1 T61 1
valid_sources[0x20] 41 1 T67 1 T162 1 T35 1
valid_sources[0x21] 76 1 T152 2 T76 1 T154 2
valid_sources[0x22] 69 1 T24 1 T30 6 T125 1
valid_sources[0x23] 100 1 T151 1 T35 1 T76 1
valid_sources[0x24] 63 1 T35 1 T125 1 T141 2
valid_sources[0x25] 73 1 T157 4 T158 1 T36 1
valid_sources[0x26] 44 1 T77 1 T118 2 T113 1
valid_sources[0x27] 150 1 T157 1 T165 1 T34 11
valid_sources[0x28] 99 1 T157 1 T35 1 T76 2
valid_sources[0x29] 102 1 T159 1 T35 1 T31 5
valid_sources[0x2a] 264 1 T167 5 T37 2 T77 2
valid_sources[0x2b] 72 1 T47 4 T154 1 T118 1
valid_sources[0x2c] 65 1 T168 1 T159 1 T154 2
valid_sources[0x2d] 91 1 T71 1 T141 2 T154 2
valid_sources[0x2e] 85 1 T24 1 T36 1 T35 1
valid_sources[0x2f] 82 1 T156 1 T165 1 T31 2
valid_sources[0x30] 72 1 T76 1 T71 1 T80 1
valid_sources[0x31] 167 1 T38 1 T71 2 T80 12
valid_sources[0x32] 61 1 T125 1 T154 1 T113 4
valid_sources[0x33] 166 1 T66 28 T71 1 T74 66
valid_sources[0x34] 72 1 T158 1 T151 1 T80 9
valid_sources[0x35] 84 1 T125 1 T141 1 T154 3
valid_sources[0x36] 68 1 T169 1 T77 1 T71 1
valid_sources[0x37] 79 1 T38 4 T170 6 T35 1
valid_sources[0x38] 138 1 T165 1 T154 2 T118 1
valid_sources[0x39] 72 1 T151 1 T36 1 T76 4
valid_sources[0x3a] 106 1 T116 1 T35 1 T77 1
valid_sources[0x3b] 80 1 T151 1 T36 1 T77 1
valid_sources[0x3c] 79 1 T74 1 T141 1 T154 2
valid_sources[0x3d] 77 1 T171 9 T159 1 T77 2
valid_sources[0x3e] 58 1 T117 1 T160 1 T84 3
valid_sources[0x3f] 93 1 T159 1 T151 1 T35 1
valid_sources[0x40] 93 1 T158 1 T76 1 T61 1
valid_sources[0x41] 217 1 T156 1 T71 1 T80 6
valid_sources[0x42] 85 1 T33 3 T71 5 T125 1
valid_sources[0x43] 98 1 T158 1 T77 1 T73 35
valid_sources[0x44] 296 1 T35 1 T76 2 T61 1
valid_sources[0x45] 56 1 T24 2 T78 2 T141 1
valid_sources[0x46] 69 1 T35 2 T71 2 T125 1
valid_sources[0x47] 64 1 T39 1 T172 1 T84 3
valid_sources[0x48] 109 1 T173 1 T174 2 T157 1
valid_sources[0x49] 90 1 T71 1 T80 7 T81 1
valid_sources[0x4a] 81 1 T76 1 T61 1 T125 2
valid_sources[0x4b] 75 1 T35 1 T141 2 T118 6
valid_sources[0x4c] 68 1 T175 1 T157 1 T141 3
valid_sources[0x4d] 125 1 T152 1 T176 1 T159 1
valid_sources[0x4e] 184 1 T157 1 T35 1 T37 6
valid_sources[0x4f] 120 1 T177 5 T76 2 T71 2
valid_sources[0x50] 100 1 T125 1 T154 2 T113 3
valid_sources[0x51] 79 1 T35 1 T76 1 T77 2
valid_sources[0x52] 55 1 T47 1 T158 1 T37 5
valid_sources[0x53] 47 1 T35 1 T71 1 T141 3
valid_sources[0x54] 63 1 T70 1 T61 1 T71 1
valid_sources[0x55] 70 1 T172 2 T77 2 T125 1
valid_sources[0x56] 196 1 T77 1 T71 1 T125 1
valid_sources[0x57] 100 1 T163 1 T71 1 T80 11
valid_sources[0x58] 79 1 T32 3 T61 1 T125 1
valid_sources[0x59] 85 1 T78 1 T80 11 T84 3
valid_sources[0x5a] 225 1 T174 2 T170 3 T34 6
valid_sources[0x5b] 77 1 T69 1 T159 1 T141 1
valid_sources[0x5c] 122 1 T151 1 T165 4 T79 1
valid_sources[0x5d] 54 1 T35 1 T76 1 T141 1
valid_sources[0x5e] 122 1 T174 1 T153 1 T170 4
valid_sources[0x5f] 88 1 T25 2 T68 1 T156 1
valid_sources[0x60] 87 1 T71 2 T125 2 T141 1
valid_sources[0x61] 63 1 T156 1 T165 1 T76 2
valid_sources[0x62] 72 1 T48 1 T61 1 T141 1
valid_sources[0x63] 126 1 T175 2 T158 1 T76 1
valid_sources[0x64] 72 1 T117 1 T31 3 T71 1
valid_sources[0x65] 99 1 T165 1 T77 1 T33 6
valid_sources[0x66] 272 1 T117 2 T32 1 T61 1
valid_sources[0x67] 94 1 T24 1 T71 1 T154 2
valid_sources[0x68] 95 1 T77 3 T32 1 T80 4
valid_sources[0x69] 93 1 T35 1 T31 2 T71 1
valid_sources[0x6a] 85 1 T155 5 T176 1 T71 1
valid_sources[0x6b] 38 1 T158 1 T35 1 T77 1
valid_sources[0x6c] 61 1 T117 3 T151 1 T125 1
valid_sources[0x6d] 146 1 T172 1 T77 1 T118 1
valid_sources[0x6e] 64 1 T69 1 T35 1 T77 1
valid_sources[0x6f] 66 1 T35 1 T77 1 T71 1
valid_sources[0x70] 68 1 T24 1 T154 2 T118 3
valid_sources[0x71] 49 1 T81 3 T154 1 T128 2
valid_sources[0x72] 98 1 T77 2 T61 2 T125 3
valid_sources[0x73] 39 1 T49 1 T35 1 T77 1
valid_sources[0x74] 71 1 T35 2 T125 1 T154 3
valid_sources[0x75] 93 1 T77 1 T33 6 T125 2
valid_sources[0x76] 58 1 T160 1 T71 2 T141 1
valid_sources[0x77] 112 1 T35 1 T77 1 T32 1
valid_sources[0x78] 141 1 T159 1 T35 1 T71 1
valid_sources[0x79] 76 1 T76 1 T33 3 T125 2
valid_sources[0x7a] 84 1 T163 4 T159 1 T31 2
valid_sources[0x7b] 72 1 T35 1 T76 5 T78 1
valid_sources[0x7c] 80 1 T159 1 T172 3 T61 1
valid_sources[0x7d] 52 1 T78 1 T118 2 T113 1
valid_sources[0x7e] 68 1 T33 11 T61 2 T80 9
valid_sources[0x7f] 52 1 T151 1 T71 1 T154 1
valid_sources[0x80] 106 1 T36 1 T31 1 T74 64



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 6839 1 T36 1 T34 34 T35 22
values[0x0] all_enables biggest_size 6598 1 T24 2 T25 1 T26 1
values[0x1] all_enables biggest_size 6386 1 T24 1 T26 2 T30 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%