Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	217641	1		T1	85		T2	1		T4	71
full_word	530052	1		T1	18		T6	2		T4	40

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	747343	1		T1	103		T2	1		T6	2
auto[TlIntgErrCmd]	125	1		T31	5		T33	7		T84	5
auto[TlIntgErrData]	126	1		T31	3		T33	6		T84	10
auto[TlIntgErrBoth]	99	1		T31	2		T33	7		T84	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	445512	1		T4	24		T15	8		T16	4
auto[1]	302181	1		T1	103		T2	1		T6	2

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	172313	1		T4	11		T15	5		T16	1
auto[TlIntgErrNone]	partial	auto[1]	45016	1		T1	85		T2	1		T4	60
auto[TlIntgErrNone]	full_word	auto[0]	273041	1		T4	13		T15	3		T16	3
auto[TlIntgErrNone]	full_word	auto[1]	256973	1		T1	18		T6	2		T4	27
auto[TlIntgErrCmd]	partial	auto[0]	47	1		T31	2		T33	4		T128	2
auto[TlIntgErrCmd]	partial	auto[1]	64	1		T31	3		T33	2		T84	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T128	1		T135	1		T129	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1		T33	1		T84	1		T132	1
auto[TlIntgErrData]	partial	auto[0]	53	1		T31	1		T33	4		T84	3
auto[TlIntgErrData]	partial	auto[1]	62	1		T31	1		T33	1		T84	7
auto[TlIntgErrData]	full_word	auto[0]	8	1		T31	1		T33	1		T128	2
auto[TlIntgErrData]	full_word	auto[1]	3	1		T136	1		T137	1		T138	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1		T31	1		T33	2		T84	4
auto[TlIntgErrBoth]	partial	auto[1]	44	1		T31	1		T33	4		T128	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T84	1		T119	1		T133	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1		T33	1		T132	1		T136	2