Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.03	90.91	61.70	87.88		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	51044615	12142	0	0
late_debug_enable_rd_A	51044615	3108	0	0
late_debug_enable_regwen_rd_A	51044615	2451	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51044615	12142	0	0
T31	46369	4	0	0
T32	256686	24	0	0
T33	124553	5	0	0
T34	4122	109	0	0
T35	8815	363	0	0
T61	360437	14	0	0
T66	20418	318	0	0
T71	10753	384	0	0
T72	94037	83	0	0
T73	42067	45	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51044615	3108	0	0
T31	46369	32	0	0
T35	8815	110	0	0
T61	360437	18	0	0
T74	169698	38	0	0
T76	40553	43	0	0
T77	39212	30	0	0
T80	365467	227	0	0
T84	88474	44	0	0
T118	317037	147	0	0
T119	97348	27	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51044615	2451	0	0
T31	46369	46	0	0
T35	8815	126	0	0
T36	5079	8	0	0
T61	360437	10	0	0
T74	169698	39	0	0
T76	40553	61	0	0
T77	39212	71	0	0
T80	365467	222	0	0
T82	5564	1	0	0
T84	88474	66	0	0