Line Coverage for Module :
tlul_adapter_host
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
CONT_ASSIGN | 115 | 1 | 1 | 100.00 |
CONT_ASSIGN | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
ALWAYS | 131 | 4 | 4 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 152 | 1 | 1 | 100.00 |
ALWAYS | 166 | 0 | 0 | |
ALWAYS | 176 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
93 |
1 |
1 |
95 |
1 |
1 |
115 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
|
|
|
MISSING_ELSE |
140 |
1 |
1 |
144 |
1 |
1 |
148 |
1 |
1 |
152 |
1 |
1 |
166 |
|
unreachable |
168 |
|
unreachable |
169 |
|
unreachable |
170 |
|
unreachable |
171 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
176 |
|
unreachable |
177 |
|
unreachable |
179 |
|
unreachable |
Cond Coverage for Module :
tlul_adapter_host
| Total | Covered | Percent |
Conditions | 12 | 12 | 100.00 |
Logical | 12 | 12 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 93
EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
----1----
-1- | Status | Tests |
0 | Covered | T8,T9,T10 |
1 | Covered | T1,T2,T3 |
LINE 95
EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
----1----
-1- | Status | Tests |
0 | Covered | T8,T9,T10 |
1 | Covered | T1,T2,T3 |
LINE 95
SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
----1----
-1- | Status | Tests |
0 | Covered | T8,T9,T10 |
1 | Covered | T8,T9,T10 |
LINE 140
EXPRESSION (tl_i.d_error | intg_err)
------1----- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T14,T15,T16 |
0 | 1 | Covered | T12,T13,T18 |
1 | 0 | Covered | T1,T2,T3 |
LINE 144
EXPRESSION (intg_err_q | intg_err)
-----1---- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T12,T13,T18 |
1 | 0 | Covered | T12,T13,T18 |
Branch Coverage for Module :
tlul_adapter_host
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
93 |
2 |
2 |
100.00 |
IF |
131 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 93 ((~we_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T8,T9,T10 |
LineNo. Expression
-1-: 131 if ((!rst_ni))
-2-: 133 if (intg_err)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T12,T13,T18 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
tlul_adapter_host
Assertion Details
DontExceeedMaxReqs
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
51044615 |
55836 |
0 |
0 |
T8 |
392275 |
529 |
0 |
0 |
T9 |
53333 |
87 |
0 |
0 |
T10 |
0 |
30 |
0 |
0 |
T12 |
0 |
533 |
0 |
0 |
T13 |
0 |
380 |
0 |
0 |
T17 |
184624 |
0 |
0 |
0 |
T18 |
0 |
1052 |
0 |
0 |
T26 |
1574 |
0 |
0 |
0 |
T27 |
12512 |
0 |
0 |
0 |
T30 |
1897 |
0 |
0 |
0 |
T38 |
2660 |
0 |
0 |
0 |
T40 |
0 |
572 |
0 |
0 |
T41 |
79441 |
0 |
0 |
0 |
T55 |
23722 |
0 |
0 |
0 |
T58 |
5139 |
0 |
0 |
0 |
T85 |
0 |
718 |
0 |
0 |
T86 |
0 |
236 |
0 |
0 |
T87 |
0 |
315 |
0 |
0 |