SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
81.44 | 96.08 | 77.78 | 100.00 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1026 | 1026 | 0 | 0 |
OutputsKnown_A | 147016110 | 146746248 | 0 | 0 |
gen_flops.OutputDelay_A | 73508055 | 73367022 | 0 | 1539 |
gen_no_flops.OutputDelay_A | 73508055 | 73373124 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1026 | 1026 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T6 | 6 | 6 | 0 | 0 |
T14 | 6 | 6 | 0 | 0 |
T15 | 6 | 6 | 0 | 0 |
T16 | 6 | 6 | 0 | 0 |
T24 | 6 | 6 | 0 | 0 |
T25 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 147016110 | 146746248 | 0 | 0 |
T1 | 1756554 | 1754334 | 0 | 0 |
T2 | 12978 | 12420 | 0 | 0 |
T3 | 35766 | 35382 | 0 | 0 |
T4 | 1876482 | 1874016 | 0 | 0 |
T6 | 17610 | 17310 | 0 | 0 |
T14 | 148332 | 148032 | 0 | 0 |
T15 | 1077750 | 1076220 | 0 | 0 |
T16 | 36306 | 35964 | 0 | 0 |
T24 | 8844 | 8376 | 0 | 0 |
T25 | 6120 | 5742 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 73508055 | 73367022 | 0 | 1539 |
T1 | 878277 | 877113 | 0 | 9 |
T2 | 6489 | 6201 | 0 | 9 |
T3 | 17883 | 17682 | 0 | 9 |
T4 | 938241 | 936954 | 0 | 9 |
T6 | 8805 | 8646 | 0 | 9 |
T14 | 74166 | 74007 | 0 | 9 |
T15 | 538875 | 538074 | 0 | 9 |
T16 | 18153 | 17973 | 0 | 9 |
T24 | 4422 | 4179 | 0 | 9 |
T25 | 3060 | 2862 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 73508055 | 73373124 | 0 | 0 |
T1 | 878277 | 877167 | 0 | 0 |
T2 | 6489 | 6210 | 0 | 0 |
T3 | 17883 | 17691 | 0 | 0 |
T4 | 938241 | 937008 | 0 | 0 |
T6 | 8805 | 8655 | 0 | 0 |
T14 | 74166 | 74016 | 0 | 0 |
T15 | 538875 | 538110 | 0 | 0 |
T16 | 18153 | 17982 | 0 | 0 |
T24 | 4422 | 4188 | 0 | 0 |
T25 | 3060 | 2871 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 171 | 171 | 0 | 0 |
OutputsKnown_A | 24502685 | 24457708 | 0 | 0 |
gen_flops.OutputDelay_A | 24502685 | 24455674 | 0 | 513 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 171 | 171 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24502685 | 24457708 | 0 | 0 |
T1 | 292759 | 292389 | 0 | 0 |
T2 | 2163 | 2070 | 0 | 0 |
T3 | 5961 | 5897 | 0 | 0 |
T4 | 312747 | 312336 | 0 | 0 |
T6 | 2935 | 2885 | 0 | 0 |
T14 | 24722 | 24672 | 0 | 0 |
T15 | 179625 | 179370 | 0 | 0 |
T16 | 6051 | 5994 | 0 | 0 |
T24 | 1474 | 1396 | 0 | 0 |
T25 | 1020 | 957 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24502685 | 24455674 | 0 | 513 |
T1 | 292759 | 292371 | 0 | 3 |
T2 | 2163 | 2067 | 0 | 3 |
T3 | 5961 | 5894 | 0 | 3 |
T4 | 312747 | 312318 | 0 | 3 |
T6 | 2935 | 2882 | 0 | 3 |
T14 | 24722 | 24669 | 0 | 3 |
T15 | 179625 | 179358 | 0 | 3 |
T16 | 6051 | 5991 | 0 | 3 |
T24 | 1474 | 1393 | 0 | 3 |
T25 | 1020 | 954 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 171 | 171 | 0 | 0 |
OutputsKnown_A | 24502685 | 24457708 | 0 | 0 |
gen_flops.OutputDelay_A | 24502685 | 24455674 | 0 | 513 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 171 | 171 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24502685 | 24457708 | 0 | 0 |
T1 | 292759 | 292389 | 0 | 0 |
T2 | 2163 | 2070 | 0 | 0 |
T3 | 5961 | 5897 | 0 | 0 |
T4 | 312747 | 312336 | 0 | 0 |
T6 | 2935 | 2885 | 0 | 0 |
T14 | 24722 | 24672 | 0 | 0 |
T15 | 179625 | 179370 | 0 | 0 |
T16 | 6051 | 5994 | 0 | 0 |
T24 | 1474 | 1396 | 0 | 0 |
T25 | 1020 | 957 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24502685 | 24455674 | 0 | 513 |
T1 | 292759 | 292371 | 0 | 3 |
T2 | 2163 | 2067 | 0 | 3 |
T3 | 5961 | 5894 | 0 | 3 |
T4 | 312747 | 312318 | 0 | 3 |
T6 | 2935 | 2882 | 0 | 3 |
T14 | 24722 | 24669 | 0 | 3 |
T15 | 179625 | 179358 | 0 | 3 |
T16 | 6051 | 5991 | 0 | 3 |
T24 | 1474 | 1393 | 0 | 3 |
T25 | 1020 | 954 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 171 | 171 | 0 | 0 |
OutputsKnown_A | 24502685 | 24457708 | 0 | 0 |
gen_no_flops.OutputDelay_A | 24502685 | 24457708 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 171 | 171 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24502685 | 24457708 | 0 | 0 |
T1 | 292759 | 292389 | 0 | 0 |
T2 | 2163 | 2070 | 0 | 0 |
T3 | 5961 | 5897 | 0 | 0 |
T4 | 312747 | 312336 | 0 | 0 |
T6 | 2935 | 2885 | 0 | 0 |
T14 | 24722 | 24672 | 0 | 0 |
T15 | 179625 | 179370 | 0 | 0 |
T16 | 6051 | 5994 | 0 | 0 |
T24 | 1474 | 1396 | 0 | 0 |
T25 | 1020 | 957 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24502685 | 24457708 | 0 | 0 |
T1 | 292759 | 292389 | 0 | 0 |
T2 | 2163 | 2070 | 0 | 0 |
T3 | 5961 | 5897 | 0 | 0 |
T4 | 312747 | 312336 | 0 | 0 |
T6 | 2935 | 2885 | 0 | 0 |
T14 | 24722 | 24672 | 0 | 0 |
T15 | 179625 | 179370 | 0 | 0 |
T16 | 6051 | 5994 | 0 | 0 |
T24 | 1474 | 1396 | 0 | 0 |
T25 | 1020 | 957 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 171 | 171 | 0 | 0 |
OutputsKnown_A | 24502685 | 24457708 | 0 | 0 |
gen_flops.OutputDelay_A | 24502685 | 24455674 | 0 | 513 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 171 | 171 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24502685 | 24457708 | 0 | 0 |
T1 | 292759 | 292389 | 0 | 0 |
T2 | 2163 | 2070 | 0 | 0 |
T3 | 5961 | 5897 | 0 | 0 |
T4 | 312747 | 312336 | 0 | 0 |
T6 | 2935 | 2885 | 0 | 0 |
T14 | 24722 | 24672 | 0 | 0 |
T15 | 179625 | 179370 | 0 | 0 |
T16 | 6051 | 5994 | 0 | 0 |
T24 | 1474 | 1396 | 0 | 0 |
T25 | 1020 | 957 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24502685 | 24455674 | 0 | 513 |
T1 | 292759 | 292371 | 0 | 3 |
T2 | 2163 | 2067 | 0 | 3 |
T3 | 5961 | 5894 | 0 | 3 |
T4 | 312747 | 312318 | 0 | 3 |
T6 | 2935 | 2882 | 0 | 3 |
T14 | 24722 | 24669 | 0 | 3 |
T15 | 179625 | 179358 | 0 | 3 |
T16 | 6051 | 5991 | 0 | 3 |
T24 | 1474 | 1393 | 0 | 3 |
T25 | 1020 | 954 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 171 | 171 | 0 | 0 |
OutputsKnown_A | 24502685 | 24457708 | 0 | 0 |
gen_no_flops.OutputDelay_A | 24502685 | 24457708 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 171 | 171 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24502685 | 24457708 | 0 | 0 |
T1 | 292759 | 292389 | 0 | 0 |
T2 | 2163 | 2070 | 0 | 0 |
T3 | 5961 | 5897 | 0 | 0 |
T4 | 312747 | 312336 | 0 | 0 |
T6 | 2935 | 2885 | 0 | 0 |
T14 | 24722 | 24672 | 0 | 0 |
T15 | 179625 | 179370 | 0 | 0 |
T16 | 6051 | 5994 | 0 | 0 |
T24 | 1474 | 1396 | 0 | 0 |
T25 | 1020 | 957 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24502685 | 24457708 | 0 | 0 |
T1 | 292759 | 292389 | 0 | 0 |
T2 | 2163 | 2070 | 0 | 0 |
T3 | 5961 | 5897 | 0 | 0 |
T4 | 312747 | 312336 | 0 | 0 |
T6 | 2935 | 2885 | 0 | 0 |
T14 | 24722 | 24672 | 0 | 0 |
T15 | 179625 | 179370 | 0 | 0 |
T16 | 6051 | 5994 | 0 | 0 |
T24 | 1474 | 1396 | 0 | 0 |
T25 | 1020 | 957 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 171 | 171 | 0 | 0 |
OutputsKnown_A | 24502685 | 24457708 | 0 | 0 |
gen_no_flops.OutputDelay_A | 24502685 | 24457708 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 171 | 171 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24502685 | 24457708 | 0 | 0 |
T1 | 292759 | 292389 | 0 | 0 |
T2 | 2163 | 2070 | 0 | 0 |
T3 | 5961 | 5897 | 0 | 0 |
T4 | 312747 | 312336 | 0 | 0 |
T6 | 2935 | 2885 | 0 | 0 |
T14 | 24722 | 24672 | 0 | 0 |
T15 | 179625 | 179370 | 0 | 0 |
T16 | 6051 | 5994 | 0 | 0 |
T24 | 1474 | 1396 | 0 | 0 |
T25 | 1020 | 957 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24502685 | 24457708 | 0 | 0 |
T1 | 292759 | 292389 | 0 | 0 |
T2 | 2163 | 2070 | 0 | 0 |
T3 | 5961 | 5897 | 0 | 0 |
T4 | 312747 | 312336 | 0 | 0 |
T6 | 2935 | 2885 | 0 | 0 |
T14 | 24722 | 24672 | 0 | 0 |
T15 | 179625 | 179370 | 0 | 0 |
T16 | 6051 | 5994 | 0 | 0 |
T24 | 1474 | 1396 | 0 | 0 |
T25 | 1020 | 957 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |