Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	176305	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	525276	1		T4	15		T5	34		T17	10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	423874	1		T4	10		T5	20		T17	6
values[0x0]	136421	1		T4	7		T5	46		T17	2
values[0x1]	141286	1		T4	6		T5	47		T17	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	135796	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	565785	1		T4	15		T5	44		T17	11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2549	1		T9	1		T32	1		T39	2
valid_sources[0x01]	4186	1		T7	1		T118	1		T31	1
valid_sources[0x02]	2456	1		T7	3		T9	3		T50	2
valid_sources[0x03]	2703	1		T54	1		T41	1		T39	6
valid_sources[0x04]	2178	1		T49	7		T7	1		T32	1
valid_sources[0x05]	3401	1		T7	1		T50	1		T31	2
valid_sources[0x06]	3461	1		T9	1		T31	1		T41	16
valid_sources[0x07]	2507	1		T31	1		T32	2		T38	1
valid_sources[0x08]	3601	1		T4	1		T7	2		T9	1
valid_sources[0x09]	3858	1		T29	1		T9	1		T41	6
valid_sources[0x0a]	2673	1		T79	1		T39	8		T80	4
valid_sources[0x0b]	2503	1		T38	5		T39	3		T80	13
valid_sources[0x0c]	3700	1		T9	1		T41	21		T38	3
valid_sources[0x0d]	2209	1		T7	7		T32	1		T38	3
valid_sources[0x0e]	2799	1		T4	2		T29	1		T9	1
valid_sources[0x0f]	3074	1		T7	1		T10	71		T140	1
valid_sources[0x10]	2475	1		T49	1		T22	1		T41	62
valid_sources[0x11]	2247	1		T29	1		T140	1		T38	3
valid_sources[0x12]	4100	1		T9	1		T41	2		T38	4
valid_sources[0x13]	6274	1		T7	2		T39	9		T80	2
valid_sources[0x14]	2471	1		T39	7		T82	7		T83	10
valid_sources[0x15]	2189	1		T7	1		T31	1		T33	9
valid_sources[0x16]	2446	1		T7	1		T9	1		T141	1
valid_sources[0x17]	2535	1		T7	4		T50	1		T39	1
valid_sources[0x18]	2503	1		T50	1		T32	3		T39	6
valid_sources[0x19]	3131	1		T41	8		T38	2		T39	8
valid_sources[0x1a]	2116	1		T6	3		T39	2		T82	6
valid_sources[0x1b]	2702	1		T39	1		T80	1		T82	5
valid_sources[0x1c]	2490	1		T9	1		T50	2		T31	1
valid_sources[0x1d]	3043	1		T7	2		T22	1		T142	3
valid_sources[0x1e]	2527	1		T7	1		T39	3		T80	12
valid_sources[0x1f]	2654	1		T7	2		T39	1		T80	2
valid_sources[0x20]	2986	1		T22	1		T32	1		T38	1
valid_sources[0x21]	2948	1		T9	1		T22	4		T38	1
valid_sources[0x22]	2746	1		T7	1		T32	1		T41	19
valid_sources[0x23]	2687	1		T6	1		T7	1		T39	1
valid_sources[0x24]	2602	1		T49	4		T70	1		T29	1
valid_sources[0x25]	2462	1		T22	1		T141	1		T38	1
valid_sources[0x26]	3078	1		T140	1		T80	7		T82	3
valid_sources[0x27]	2812	1		T29	1		T9	1		T50	1
valid_sources[0x28]	2910	1		T29	1		T9	1		T50	1
valid_sources[0x29]	3641	1		T41	13		T38	2		T39	3
valid_sources[0x2a]	2942	1		T30	57		T22	1		T141	5
valid_sources[0x2b]	2573	1		T9	1		T39	9		T82	5
valid_sources[0x2c]	2840	1		T9	1		T142	2		T141	5
valid_sources[0x2d]	2622	1		T32	1		T141	4		T39	2
valid_sources[0x2e]	2639	1		T5	2		T7	2		T9	3
valid_sources[0x2f]	2176	1		T7	1		T141	5		T39	2
valid_sources[0x30]	2734	1		T17	12		T50	1		T32	1
valid_sources[0x31]	3319	1		T4	1		T50	1		T39	5
valid_sources[0x32]	2864	1		T9	1		T39	3		T80	1
valid_sources[0x33]	2042	1		T32	1		T141	1		T39	1
valid_sources[0x34]	2872	1		T7	1		T9	1		T31	1
valid_sources[0x35]	2085	1		T31	1		T39	1		T83	15
valid_sources[0x36]	2636	1		T7	1		T9	2		T22	1
valid_sources[0x37]	2981	1		T9	1		T141	2		T39	8
valid_sources[0x38]	2156	1		T29	1		T9	1		T39	2
valid_sources[0x39]	2440	1		T118	1		T39	1		T82	2
valid_sources[0x3a]	4485	1		T7	1		T39	2		T81	12
valid_sources[0x3b]	3102	1		T7	3		T32	1		T38	1
valid_sources[0x3c]	2349	1		T38	1		T39	6		T82	4
valid_sources[0x3d]	2469	1		T29	1		T9	2		T22	1
valid_sources[0x3e]	2011	1		T9	1		T22	1		T32	3
valid_sources[0x3f]	2684	1		T9	2		T53	5		T32	1
valid_sources[0x40]	2588	1		T4	5		T50	1		T41	2
valid_sources[0x41]	2372	1		T7	1		T32	1		T39	8
valid_sources[0x42]	2396	1		T7	3		T9	1		T32	1
valid_sources[0x43]	2591	1		T29	2		T9	2		T41	3
valid_sources[0x44]	2336	1		T51	7		T9	2		T50	1
valid_sources[0x45]	3793	1		T7	1		T35	5		T39	3
valid_sources[0x46]	2464	1		T7	2		T9	3		T31	4
valid_sources[0x47]	2252	1		T4	4		T9	1		T31	1
valid_sources[0x48]	11059	1		T9	1		T39	3		T82	6
valid_sources[0x49]	3401	1		T9	1		T39	11		T81	22
valid_sources[0x4a]	2319	1		T7	3		T9	2		T50	1
valid_sources[0x4b]	2884	1		T9	2		T32	1		T41	6
valid_sources[0x4c]	2562	1		T9	1		T31	1		T22	1
valid_sources[0x4d]	2810	1		T32	2		T39	6		T81	71
valid_sources[0x4e]	2323	1		T143	2		T50	1		T31	1
valid_sources[0x4f]	3033	1		T9	2		T142	1		T41	8
valid_sources[0x50]	3097	1		T142	4		T39	3		T82	2
valid_sources[0x51]	2364	1		T5	43		T38	2		T39	7
valid_sources[0x52]	2153	1		T7	6		T9	1		T39	1
valid_sources[0x53]	2783	1		T7	1		T9	2		T33	2
valid_sources[0x54]	3128	1		T49	1		T7	4		T9	4
valid_sources[0x55]	2077	1		T9	3		T39	8		T82	1
valid_sources[0x56]	2421	1		T49	1		T9	1		T50	1
valid_sources[0x57]	2994	1		T70	1		T35	440		T39	1
valid_sources[0x58]	2244	1		T32	1		T39	9		T82	4
valid_sources[0x59]	2368	1		T50	1		T38	2		T39	4
valid_sources[0x5a]	2893	1		T32	1		T141	1		T39	3
valid_sources[0x5b]	2788	1		T7	1		T32	1		T35	275
valid_sources[0x5c]	4192	1		T9	1		T50	2		T39	6
valid_sources[0x5d]	2036	1		T7	1		T32	1		T140	1
valid_sources[0x5e]	2829	1		T9	3		T141	2		T33	7
valid_sources[0x5f]	2652	1		T32	3		T41	1		T38	4
valid_sources[0x60]	2555	1		T9	1		T50	1		T142	1
valid_sources[0x61]	2860	1		T9	2		T31	1		T32	2
valid_sources[0x62]	2193	1		T7	3		T29	1		T50	2
valid_sources[0x63]	2631	1		T4	1		T31	1		T142	1
valid_sources[0x64]	3051	1		T4	3		T7	1		T9	2
valid_sources[0x65]	2232	1		T9	3		T50	2		T140	1
valid_sources[0x66]	2593	1		T9	2		T50	1		T31	1
valid_sources[0x67]	2714	1		T32	1		T41	15		T80	2
valid_sources[0x68]	2934	1		T9	1		T38	1		T39	2
valid_sources[0x69]	3276	1		T82	7		T83	10		T37	1
valid_sources[0x6a]	2342	1		T50	1		T31	2		T38	3
valid_sources[0x6b]	2690	1		T9	3		T39	3		T80	1
valid_sources[0x6c]	2278	1		T49	6		T50	1		T79	1
valid_sources[0x6d]	2877	1		T31	2		T38	1		T39	1
valid_sources[0x6e]	2733	1		T7	2		T39	14		T81	2
valid_sources[0x6f]	2707	1		T31	2		T32	1		T142	2
valid_sources[0x70]	3121	1		T32	1		T38	1		T39	11
valid_sources[0x71]	2322	1		T38	2		T82	9		T83	13
valid_sources[0x72]	2671	1		T33	2		T38	2		T80	11
valid_sources[0x73]	2867	1		T31	2		T32	2		T41	2
valid_sources[0x74]	2316	1		T7	2		T33	4		T41	31
valid_sources[0x75]	2054	1		T29	1		T9	1		T32	3
valid_sources[0x76]	2637	1		T31	1		T140	1		T39	1
valid_sources[0x77]	2555	1		T9	1		T35	186		T39	3
valid_sources[0x78]	2641	1		T31	1		T32	1		T38	1
valid_sources[0x79]	3153	1		T7	1		T118	1		T141	2
valid_sources[0x7a]	2529	1		T5	14		T141	1		T38	6
valid_sources[0x7b]	2390	1		T9	1		T144	8		T32	1
valid_sources[0x7c]	2653	1		T4	1		T38	1		T39	7
valid_sources[0x7d]	2783	1		T7	1		T9	6		T38	2
valid_sources[0x7e]	2175	1		T5	31		T50	2		T32	1
valid_sources[0x7f]	2709	1		T7	1		T9	1		T39	2
valid_sources[0x80]	2860	1		T7	1		T9	1		T32	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

256553

1

T4

5

T5

8

T17

4

values[0x0]

all_enables

biggest_size

134529

1

T4

7

T5

18

T17

2

values[0x1]

all_enables

biggest_size

134194

1

T4

3

T5

8

T17

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3929	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	16900	1		T3	5		T27	1		T28	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7247	1		T41	3		T38	48		T35	120
values[0x0]	6597	1		T3	8		T27	8		T42	6
values[0x1]	6985	1		T3	3		T27	3		T28	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2942	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	17887	1		T3	7		T27	1		T28	2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49	1		T145	1		T65	3		T66	1
valid_sources[0x01]	63	1		T37	6		T65	5		T66	1
valid_sources[0x02]	92	1		T35	17		T37	1		T65	2
valid_sources[0x03]	55	1		T146	1		T65	3		T72	3
valid_sources[0x04]	62	1		T147	1		T65	3		T73	3
valid_sources[0x05]	66	1		T65	1		T66	3		T72	1
valid_sources[0x06]	88	1		T147	1		T35	6		T65	2
valid_sources[0x07]	52	1		T35	1		T65	2		T66	6
valid_sources[0x08]	86	1		T145	1		T65	2		T72	1
valid_sources[0x09]	61	1		T65	2		T66	2		T86	1
valid_sources[0x0a]	64	1		T35	1		T65	4		T66	1
valid_sources[0x0b]	79	1		T147	1		T120	1		T60	3
valid_sources[0x0c]	58	1		T82	1		T72	6		T87	1
valid_sources[0x0d]	81	1		T65	2		T66	2		T87	3
valid_sources[0x0e]	170	1		T41	1		T38	3		T35	8
valid_sources[0x0f]	83	1		T148	1		T38	7		T65	2
valid_sources[0x10]	90	1		T65	1		T66	1		T72	3
valid_sources[0x11]	105	1		T43	1		T35	4		T36	1
valid_sources[0x12]	53	1		T65	2		T66	2		T71	1
valid_sources[0x13]	71	1		T147	1		T149	1		T35	3
valid_sources[0x14]	74	1		T47	7		T65	1		T109	1
valid_sources[0x15]	67	1		T35	3		T66	1		T109	1
valid_sources[0x16]	81	1		T150	1		T38	9		T65	3
valid_sources[0x17]	74	1		T65	2		T66	6		T71	2
valid_sources[0x18]	106	1		T146	1		T38	3		T35	7
valid_sources[0x19]	54	1		T36	1		T66	1		T87	1
valid_sources[0x1a]	74	1		T128	1		T65	1		T72	2
valid_sources[0x1b]	75	1		T35	3		T36	4		T65	1
valid_sources[0x1c]	53	1		T147	1		T151	1		T66	1
valid_sources[0x1d]	62	1		T65	1		T66	9		T85	1
valid_sources[0x1e]	74	1		T47	2		T149	1		T65	2
valid_sources[0x1f]	92	1		T152	10		T35	7		T66	2
valid_sources[0x20]	93	1		T128	1		T65	2		T66	3
valid_sources[0x21]	70	1		T153	2		T35	1		T36	1
valid_sources[0x22]	68	1		T154	1		T65	2		T87	1
valid_sources[0x23]	140	1		T82	1		T71	2		T109	1
valid_sources[0x24]	102	1		T77	1		T155	1		T151	1
valid_sources[0x25]	73	1		T65	4		T66	3		T71	1
valid_sources[0x26]	72	1		T155	1		T83	15		T65	2
valid_sources[0x27]	97	1		T38	18		T65	2		T156	2
valid_sources[0x28]	70	1		T146	1		T157	1		T65	3
valid_sources[0x29]	67	1		T147	1		T65	3		T66	1
valid_sources[0x2a]	97	1		T158	3		T38	9		T65	6
valid_sources[0x2b]	60	1		T35	6		T65	1		T87	1
valid_sources[0x2c]	55	1		T148	2		T35	2		T36	2
valid_sources[0x2d]	107	1		T36	2		T66	6		T121	1
valid_sources[0x2e]	56	1		T159	1		T109	1		T87	5
valid_sources[0x2f]	51	1		T35	6		T65	4		T72	2
valid_sources[0x30]	100	1		T65	2		T71	2		T72	9
valid_sources[0x31]	71	1		T160	1		T150	4		T65	2
valid_sources[0x32]	76	1		T148	1		T161	1		T35	1
valid_sources[0x33]	48	1		T65	2		T86	1		T109	1
valid_sources[0x34]	126	1		T150	1		T35	25		T84	3
valid_sources[0x35]	55	1		T162	2		T36	2		T65	3
valid_sources[0x36]	67	1		T65	4		T66	3		T71	1
valid_sources[0x37]	110	1		T128	1		T35	5		T65	5
valid_sources[0x38]	59	1		T163	4		T66	2		T87	1
valid_sources[0x39]	82	1		T35	3		T65	3		T72	3
valid_sources[0x3a]	77	1		T64	1		T146	1		T148	3
valid_sources[0x3b]	88	1		T27	9		T64	1		T153	2
valid_sources[0x3c]	57	1		T3	9		T159	1		T65	2
valid_sources[0x3d]	57	1		T35	9		T87	3		T121	3
valid_sources[0x3e]	86	1		T164	4		T157	1		T65	1
valid_sources[0x3f]	187	1		T65	5		T71	4		T72	12
valid_sources[0x40]	88	1		T65	3		T66	3		T72	7
valid_sources[0x41]	92	1		T35	3		T72	8		T60	1
valid_sources[0x42]	66	1		T165	2		T166	1		T35	3
valid_sources[0x43]	78	1		T28	4		T65	2		T71	2
valid_sources[0x44]	96	1		T41	1		T40	4		T65	1
valid_sources[0x45]	43	1		T71	4		T60	1		T156	1
valid_sources[0x46]	74	1		T150	1		T157	1		T80	1
valid_sources[0x47]	77	1		T35	6		T36	1		T66	2
valid_sources[0x48]	60	1		T146	1		T167	3		T165	1
valid_sources[0x49]	75	1		T66	2		T76	5		T168	1
valid_sources[0x4a]	98	1		T35	10		T65	2		T71	1
valid_sources[0x4b]	53	1		T82	1		T65	5		T76	3
valid_sources[0x4c]	88	1		T147	1		T66	1		T71	1
valid_sources[0x4d]	78	1		T157	1		T166	1		T35	1
valid_sources[0x4e]	105	1		T157	1		T161	1		T35	29
valid_sources[0x4f]	55	1		T65	1		T66	1		T71	1
valid_sources[0x50]	83	1		T35	4		T66	5		T71	1
valid_sources[0x51]	126	1		T65	1		T66	3		T72	8
valid_sources[0x52]	80	1		T35	4		T66	6		T121	1
valid_sources[0x53]	93	1		T163	1		T65	1		T73	11
valid_sources[0x54]	103	1		T64	1		T65	3		T66	4
valid_sources[0x55]	102	1		T159	1		T65	1		T66	3
valid_sources[0x56]	56	1		T65	6		T66	1		T72	8
valid_sources[0x57]	68	1		T35	4		T65	2		T72	12
valid_sources[0x58]	72	1		T35	1		T65	1		T66	3
valid_sources[0x59]	85	1		T36	1		T66	2		T71	1
valid_sources[0x5a]	81	1		T169	2		T154	1		T35	14
valid_sources[0x5b]	68	1		T146	1		T35	2		T65	1
valid_sources[0x5c]	55	1		T169	2		T65	4		T66	5
valid_sources[0x5d]	67	1		T42	1		T71	1		T76	1
valid_sources[0x5e]	65	1		T160	1		T163	1		T65	1
valid_sources[0x5f]	84	1		T155	2		T163	1		T66	1
valid_sources[0x60]	65	1		T43	5		T157	1		T81	1
valid_sources[0x61]	70	1		T159	1		T170	1		T65	2
valid_sources[0x62]	89	1		T64	1		T159	1		T35	6
valid_sources[0x63]	83	1		T119	11		T153	1		T80	1
valid_sources[0x64]	213	1		T65	2		T66	3		T71	1
valid_sources[0x65]	70	1		T155	3		T35	1		T36	1
valid_sources[0x66]	95	1		T159	2		T65	1		T72	4
valid_sources[0x67]	97	1		T65	2		T66	7		T71	1
valid_sources[0x68]	114	1		T38	10		T35	12		T65	2
valid_sources[0x69]	87	1		T38	6		T37	26		T65	2
valid_sources[0x6a]	84	1		T146	1		T65	1		T72	11
valid_sources[0x6b]	121	1		T38	24		T65	3		T66	1
valid_sources[0x6c]	57	1		T65	3		T66	1		T71	6
valid_sources[0x6d]	64	1		T169	1		T41	1		T81	1
valid_sources[0x6e]	89	1		T67	7		T171	1		T36	1
valid_sources[0x6f]	98	1		T172	1		T157	1		T171	2
valid_sources[0x70]	60	1		T157	2		T171	2		T65	3
valid_sources[0x71]	65	1		T145	1		T109	1		T76	2
valid_sources[0x72]	63	1		T35	6		T87	2		T156	3
valid_sources[0x73]	76	1		T63	1		T81	1		T65	1
valid_sources[0x74]	48	1		T72	3		T87	3		T156	3
valid_sources[0x75]	72	1		T120	1		T35	6		T36	1
valid_sources[0x76]	113	1		T128	1		T65	2		T72	2
valid_sources[0x77]	87	1		T75	2		T121	2		T60	1
valid_sources[0x78]	47	1		T65	3		T71	1		T72	6
valid_sources[0x79]	40	1		T35	1		T65	2		T66	1
valid_sources[0x7a]	90	1		T151	1		T38	12		T35	6
valid_sources[0x7b]	105	1		T36	3		T37	6		T72	2
valid_sources[0x7c]	82	1		T35	1		T81	1		T66	2
valid_sources[0x7d]	85	1		T64	1		T147	1		T149	1
valid_sources[0x7e]	71	1		T3	1		T165	2		T38	11
valid_sources[0x7f]	63	1		T166	1		T35	6		T65	1
valid_sources[0x80]	70	1		T65	6		T66	5		T71	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5205

1

T41

2

T38

46

T35

109

values[0x0]

all_enables

biggest_size

5861

1

T3

5

T42

1

T47

2

values[0x1]

all_enables

biggest_size

5834

1

T27

1

T28

1

T42

2