SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 724837 | 1 | T4 | 23 | T5 | 113 | T17 | 12 | |||
auto[1] | 17433 | 1 | T49 | 80 | T50 | 80 | T38 | 522 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 742076 | 1 | T4 | 23 | T5 | 113 | T17 | 12 | |||
values[1] | 23 | 1 | T71 | 3 | T73 | 1 | T124 | 1 | |||
values[2] | 1 | 1 | T121 | 1 | - | - | - | - | |||
values[3] | 97 | 1 | T71 | 7 | T73 | 2 | T75 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 742081 | 1 | T4 | 23 | T5 | 113 | T17 | 12 | |||
values[1] | 21 | 1 | T71 | 1 | T73 | 1 | T75 | 1 | |||
values[2] | 6 | 1 | T73 | 3 | T121 | 2 | T131 | 1 | |||
values[3] | 91 | 1 | T71 | 8 | T73 | 4 | T75 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 741980 | 1 | T4 | 23 | T5 | 113 | T17 | 12 | |||
auto[TlIntgErrCmd] | 101 | 1 | T71 | 8 | T73 | 6 | T75 | 4 | |||
auto[TlIntgErrData] | 96 | 1 | T71 | 7 | T73 | 7 | T75 | 3 | |||
auto[TlIntgErrBoth] | 93 | 1 | T71 | 5 | T73 | 7 | T75 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 37754 | 0 | T3 | 11 | T27 | 11 | T28 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 37556 | 1 | T3 | 11 | T27 | 11 | T28 | 4 | |||
values[1] | 18 | 1 | T71 | 2 | T75 | 2 | T123 | 2 | |||
values[2] | 4 | 1 | T71 | 1 | T73 | 1 | T132 | 2 | |||
values[3] | 102 | 1 | T71 | 8 | T73 | 6 | T75 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 37564 | 1 | T3 | 11 | T27 | 11 | T28 | 4 | |||
values[1] | 29 | 1 | T71 | 3 | T73 | 1 | T75 | 2 | |||
values[2] | 3 | 1 | T121 | 1 | T133 | 1 | T134 | 1 | |||
values[3] | 88 | 1 | T71 | 3 | T73 | 6 | T75 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 37464 | 1 | T3 | 11 | T27 | 11 | T28 | 4 | |||
auto[TlIntgErrCmd] | 100 | 1 | T71 | 9 | T73 | 10 | T75 | 3 | |||
auto[TlIntgErrData] | 92 | 1 | T71 | 5 | T73 | 7 | T75 | 4 | |||
auto[TlIntgErrBoth] | 98 | 1 | T71 | 6 | T73 | 3 | T75 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |