Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	215458	1		T4	8		T5	79		T17	2
full_word	526812	1		T4	15		T5	34		T17	10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	741980	1		T4	23		T5	113		T17	12
auto[TlIntgErrCmd]	101	1		T71	8		T73	6		T75	4
auto[TlIntgErrData]	96	1		T71	7		T73	7		T75	3
auto[TlIntgErrBoth]	93	1		T71	5		T73	7		T75	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	425730	1		T4	10		T5	20		T17	6
auto[1]	316540	1		T4	13		T5	93		T17	6

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	168881	1		T4	5		T5	12		T17	2
auto[TlIntgErrNone]	partial	auto[1]	46313	1		T4	3		T5	67		T6	7
auto[TlIntgErrNone]	full_word	auto[0]	256725	1		T4	5		T5	8		T17	4
auto[TlIntgErrNone]	full_word	auto[1]	270061	1		T4	10		T5	26		T17	6
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T71	2		T73	3		T123	2
auto[TlIntgErrCmd]	partial	auto[1]	50	1		T71	5		T73	3		T75	3
auto[TlIntgErrCmd]	full_word	auto[0]	8	1		T71	1		T75	1		T123	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T135	1		T131	1		T136	2
auto[TlIntgErrData]	partial	auto[0]	40	1		T71	3		T73	3		T75	1
auto[TlIntgErrData]	partial	auto[1]	49	1		T71	3		T73	3		T75	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T71	1		T73	1		T135	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T137	1		T134	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	28	1		T71	3		T73	2		T75	2
auto[TlIntgErrBoth]	partial	auto[1]	59	1		T71	2		T73	5		T75	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T124	1		T138	2		T139	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T139	1		-	-		-	-