Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.03	90.91	61.70	87.88		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	51538442	13511	0	0
late_debug_enable_rd_A	51538442	2286	0	0
late_debug_enable_regwen_rd_A	51538442	2073	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51538442	13511	0	0
T35	5588	316	0	0
T36	357123	13	0	0
T37	35963	44	0	0
T38	4218	343	0	0
T65	17849	466	0	0
T66	168831	254	0	0
T71	91115	10	0	0
T72	118833	336	0	0
T73	33480	3	0	0
T74	5713	451	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51538442	2286	0	0
T37	35963	41	0	0
T71	91115	86	0	0
T83	21256	2	0	0
T85	4490	1	0	0
T117	6546	5	0	0
T121	84874	53	0	0
T122	378985	58	0	0
T123	106778	17	0	0
T124	44254	35	0	0
T125	517239	24	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51538442	2073	0	0
T37	35963	27	0	0
T39	7640	3	0	0
T71	91115	68	0	0
T83	21256	6	0	0
T85	4490	7	0	0
T121	84874	57	0	0
T122	378985	47	0	0
T123	106778	13	0	0
T124	44254	37	0	0
T125	517239	36	0	0