SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 166 | 166 | 0 | 0 |
OutputsKnown_A | 29385343 | 29335272 | 0 | 0 |
gen_no_flops.OutputDelay_A | 29385343 | 29335272 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 166 | 166 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 29385343 | 29335272 | 0 | 0 |
T1 | 18047 | 17956 | 0 | 0 |
T2 | 1522 | 1470 | 0 | 0 |
T3 | 1972 | 1917 | 0 | 0 |
T4 | 70455 | 70120 | 0 | 0 |
T8 | 46940 | 46889 | 0 | 0 |
T11 | 97996 | 97929 | 0 | 0 |
T12 | 39071 | 38568 | 0 | 0 |
T24 | 5723 | 4991 | 0 | 0 |
T27 | 1308 | 1228 | 0 | 0 |
T28 | 1078 | 1009 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 29385343 | 29335272 | 0 | 0 |
T1 | 18047 | 17956 | 0 | 0 |
T2 | 1522 | 1470 | 0 | 0 |
T3 | 1972 | 1917 | 0 | 0 |
T4 | 70455 | 70120 | 0 | 0 |
T8 | 46940 | 46889 | 0 | 0 |
T11 | 97996 | 97929 | 0 | 0 |
T12 | 39071 | 38568 | 0 | 0 |
T24 | 5723 | 4991 | 0 | 0 |
T27 | 1308 | 1228 | 0 | 0 |
T28 | 1078 | 1009 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |