SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
81.44 | 96.08 | 77.78 | 100.00 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 996 | 996 | 0 | 0 |
OutputsKnown_A | 176312058 | 176011632 | 0 | 0 |
gen_flops.OutputDelay_A | 88156029 | 87999093 | 0 | 1494 |
gen_no_flops.OutputDelay_A | 88156029 | 88005816 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 996 | 996 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T8 | 6 | 6 | 0 | 0 |
T11 | 6 | 6 | 0 | 0 |
T12 | 6 | 6 | 0 | 0 |
T24 | 6 | 6 | 0 | 0 |
T27 | 6 | 6 | 0 | 0 |
T28 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 176312058 | 176011632 | 0 | 0 |
T1 | 108282 | 107736 | 0 | 0 |
T2 | 9132 | 8820 | 0 | 0 |
T3 | 11832 | 11502 | 0 | 0 |
T4 | 422730 | 420720 | 0 | 0 |
T8 | 281640 | 281334 | 0 | 0 |
T11 | 587976 | 587574 | 0 | 0 |
T12 | 234426 | 231408 | 0 | 0 |
T24 | 34338 | 29946 | 0 | 0 |
T27 | 7848 | 7368 | 0 | 0 |
T28 | 6468 | 6054 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 88156029 | 87999093 | 0 | 1494 |
T1 | 54141 | 53859 | 0 | 9 |
T2 | 4566 | 4401 | 0 | 9 |
T3 | 5916 | 5742 | 0 | 9 |
T4 | 211365 | 210315 | 0 | 9 |
T8 | 140820 | 140658 | 0 | 9 |
T11 | 293988 | 293778 | 0 | 9 |
T12 | 117213 | 115641 | 0 | 9 |
T24 | 17169 | 14874 | 0 | 9 |
T27 | 3924 | 3675 | 0 | 9 |
T28 | 3234 | 3018 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 88156029 | 88005816 | 0 | 0 |
T1 | 54141 | 53868 | 0 | 0 |
T2 | 4566 | 4410 | 0 | 0 |
T3 | 5916 | 5751 | 0 | 0 |
T4 | 211365 | 210360 | 0 | 0 |
T8 | 140820 | 140667 | 0 | 0 |
T11 | 293988 | 293787 | 0 | 0 |
T12 | 117213 | 115704 | 0 | 0 |
T24 | 17169 | 14973 | 0 | 0 |
T27 | 3924 | 3684 | 0 | 0 |
T28 | 3234 | 3027 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 166 | 166 | 0 | 0 |
OutputsKnown_A | 29385343 | 29335272 | 0 | 0 |
gen_flops.OutputDelay_A | 29385343 | 29333031 | 0 | 498 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 166 | 166 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 29385343 | 29335272 | 0 | 0 |
T1 | 18047 | 17956 | 0 | 0 |
T2 | 1522 | 1470 | 0 | 0 |
T3 | 1972 | 1917 | 0 | 0 |
T4 | 70455 | 70120 | 0 | 0 |
T8 | 46940 | 46889 | 0 | 0 |
T11 | 97996 | 97929 | 0 | 0 |
T12 | 39071 | 38568 | 0 | 0 |
T24 | 5723 | 4991 | 0 | 0 |
T27 | 1308 | 1228 | 0 | 0 |
T28 | 1078 | 1009 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 29385343 | 29333031 | 0 | 498 |
T1 | 18047 | 17953 | 0 | 3 |
T2 | 1522 | 1467 | 0 | 3 |
T3 | 1972 | 1914 | 0 | 3 |
T4 | 70455 | 70105 | 0 | 3 |
T8 | 46940 | 46886 | 0 | 3 |
T11 | 97996 | 97926 | 0 | 3 |
T12 | 39071 | 38547 | 0 | 3 |
T24 | 5723 | 4958 | 0 | 3 |
T27 | 1308 | 1225 | 0 | 3 |
T28 | 1078 | 1006 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 166 | 166 | 0 | 0 |
OutputsKnown_A | 29385343 | 29335272 | 0 | 0 |
gen_flops.OutputDelay_A | 29385343 | 29333031 | 0 | 498 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 166 | 166 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 29385343 | 29335272 | 0 | 0 |
T1 | 18047 | 17956 | 0 | 0 |
T2 | 1522 | 1470 | 0 | 0 |
T3 | 1972 | 1917 | 0 | 0 |
T4 | 70455 | 70120 | 0 | 0 |
T8 | 46940 | 46889 | 0 | 0 |
T11 | 97996 | 97929 | 0 | 0 |
T12 | 39071 | 38568 | 0 | 0 |
T24 | 5723 | 4991 | 0 | 0 |
T27 | 1308 | 1228 | 0 | 0 |
T28 | 1078 | 1009 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 29385343 | 29333031 | 0 | 498 |
T1 | 18047 | 17953 | 0 | 3 |
T2 | 1522 | 1467 | 0 | 3 |
T3 | 1972 | 1914 | 0 | 3 |
T4 | 70455 | 70105 | 0 | 3 |
T8 | 46940 | 46886 | 0 | 3 |
T11 | 97996 | 97926 | 0 | 3 |
T12 | 39071 | 38547 | 0 | 3 |
T24 | 5723 | 4958 | 0 | 3 |
T27 | 1308 | 1225 | 0 | 3 |
T28 | 1078 | 1006 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 166 | 166 | 0 | 0 |
OutputsKnown_A | 29385343 | 29335272 | 0 | 0 |
gen_no_flops.OutputDelay_A | 29385343 | 29335272 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 166 | 166 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 29385343 | 29335272 | 0 | 0 |
T1 | 18047 | 17956 | 0 | 0 |
T2 | 1522 | 1470 | 0 | 0 |
T3 | 1972 | 1917 | 0 | 0 |
T4 | 70455 | 70120 | 0 | 0 |
T8 | 46940 | 46889 | 0 | 0 |
T11 | 97996 | 97929 | 0 | 0 |
T12 | 39071 | 38568 | 0 | 0 |
T24 | 5723 | 4991 | 0 | 0 |
T27 | 1308 | 1228 | 0 | 0 |
T28 | 1078 | 1009 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 29385343 | 29335272 | 0 | 0 |
T1 | 18047 | 17956 | 0 | 0 |
T2 | 1522 | 1470 | 0 | 0 |
T3 | 1972 | 1917 | 0 | 0 |
T4 | 70455 | 70120 | 0 | 0 |
T8 | 46940 | 46889 | 0 | 0 |
T11 | 97996 | 97929 | 0 | 0 |
T12 | 39071 | 38568 | 0 | 0 |
T24 | 5723 | 4991 | 0 | 0 |
T27 | 1308 | 1228 | 0 | 0 |
T28 | 1078 | 1009 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 166 | 166 | 0 | 0 |
OutputsKnown_A | 29385343 | 29335272 | 0 | 0 |
gen_flops.OutputDelay_A | 29385343 | 29333031 | 0 | 498 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 166 | 166 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 29385343 | 29335272 | 0 | 0 |
T1 | 18047 | 17956 | 0 | 0 |
T2 | 1522 | 1470 | 0 | 0 |
T3 | 1972 | 1917 | 0 | 0 |
T4 | 70455 | 70120 | 0 | 0 |
T8 | 46940 | 46889 | 0 | 0 |
T11 | 97996 | 97929 | 0 | 0 |
T12 | 39071 | 38568 | 0 | 0 |
T24 | 5723 | 4991 | 0 | 0 |
T27 | 1308 | 1228 | 0 | 0 |
T28 | 1078 | 1009 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 29385343 | 29333031 | 0 | 498 |
T1 | 18047 | 17953 | 0 | 3 |
T2 | 1522 | 1467 | 0 | 3 |
T3 | 1972 | 1914 | 0 | 3 |
T4 | 70455 | 70105 | 0 | 3 |
T8 | 46940 | 46886 | 0 | 3 |
T11 | 97996 | 97926 | 0 | 3 |
T12 | 39071 | 38547 | 0 | 3 |
T24 | 5723 | 4958 | 0 | 3 |
T27 | 1308 | 1225 | 0 | 3 |
T28 | 1078 | 1006 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 166 | 166 | 0 | 0 |
OutputsKnown_A | 29385343 | 29335272 | 0 | 0 |
gen_no_flops.OutputDelay_A | 29385343 | 29335272 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 166 | 166 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 29385343 | 29335272 | 0 | 0 |
T1 | 18047 | 17956 | 0 | 0 |
T2 | 1522 | 1470 | 0 | 0 |
T3 | 1972 | 1917 | 0 | 0 |
T4 | 70455 | 70120 | 0 | 0 |
T8 | 46940 | 46889 | 0 | 0 |
T11 | 97996 | 97929 | 0 | 0 |
T12 | 39071 | 38568 | 0 | 0 |
T24 | 5723 | 4991 | 0 | 0 |
T27 | 1308 | 1228 | 0 | 0 |
T28 | 1078 | 1009 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 29385343 | 29335272 | 0 | 0 |
T1 | 18047 | 17956 | 0 | 0 |
T2 | 1522 | 1470 | 0 | 0 |
T3 | 1972 | 1917 | 0 | 0 |
T4 | 70455 | 70120 | 0 | 0 |
T8 | 46940 | 46889 | 0 | 0 |
T11 | 97996 | 97929 | 0 | 0 |
T12 | 39071 | 38568 | 0 | 0 |
T24 | 5723 | 4991 | 0 | 0 |
T27 | 1308 | 1228 | 0 | 0 |
T28 | 1078 | 1009 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 166 | 166 | 0 | 0 |
OutputsKnown_A | 29385343 | 29335272 | 0 | 0 |
gen_no_flops.OutputDelay_A | 29385343 | 29335272 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 166 | 166 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 29385343 | 29335272 | 0 | 0 |
T1 | 18047 | 17956 | 0 | 0 |
T2 | 1522 | 1470 | 0 | 0 |
T3 | 1972 | 1917 | 0 | 0 |
T4 | 70455 | 70120 | 0 | 0 |
T8 | 46940 | 46889 | 0 | 0 |
T11 | 97996 | 97929 | 0 | 0 |
T12 | 39071 | 38568 | 0 | 0 |
T24 | 5723 | 4991 | 0 | 0 |
T27 | 1308 | 1228 | 0 | 0 |
T28 | 1078 | 1009 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 29385343 | 29335272 | 0 | 0 |
T1 | 18047 | 17956 | 0 | 0 |
T2 | 1522 | 1470 | 0 | 0 |
T3 | 1972 | 1917 | 0 | 0 |
T4 | 70455 | 70120 | 0 | 0 |
T8 | 46940 | 46889 | 0 | 0 |
T11 | 97996 | 97929 | 0 | 0 |
T12 | 39071 | 38568 | 0 | 0 |
T24 | 5723 | 4991 | 0 | 0 |
T27 | 1308 | 1228 | 0 | 0 |
T28 | 1078 | 1009 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |