Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 203505 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 573548 1 T2 12 T3 80 T5 22



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 478788 1 T2 6 T3 80 T6 48
values[0x0] 146643 1 T2 16 T5 32 T6 32
values[0x1] 151622 1 T2 14 T5 35 T6 32



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 156263 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 620790 1 T2 19 T3 80 T5 26



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2896 1 T70 1 T71 2 T23 1
valid_sources[0x01] 3010 1 T2 1 T39 1 T70 1
valid_sources[0x02] 3249 1 T3 2 T12 1 T109 88
valid_sources[0x03] 3009 1 T9 1 T70 1 T72 3
valid_sources[0x04] 2548 1 T8 2 T23 1 T44 1
valid_sources[0x05] 3157 1 T12 1 T39 2 T9 2
valid_sources[0x06] 3048 1 T39 1 T23 2 T109 92
valid_sources[0x07] 2736 1 T23 1 T109 104 T25 3
valid_sources[0x08] 2992 1 T3 1 T44 1 T109 104
valid_sources[0x09] 2710 1 T12 3 T49 1 T9 1
valid_sources[0x0a] 3018 1 T12 1 T39 1 T9 1
valid_sources[0x0b] 3155 1 T5 1 T12 1 T39 1
valid_sources[0x0c] 2755 1 T2 1 T3 2 T70 1
valid_sources[0x0d] 2864 1 T12 3 T39 1 T117 1
valid_sources[0x0e] 2446 1 T12 1 T109 87 T28 20
valid_sources[0x0f] 2889 1 T3 2 T12 1 T39 1
valid_sources[0x10] 2888 1 T39 1 T9 2 T44 1
valid_sources[0x11] 2534 1 T48 1 T117 1 T136 1
valid_sources[0x12] 4253 1 T49 1 T44 6 T109 114
valid_sources[0x13] 3109 1 T48 1 T109 112 T25 1
valid_sources[0x14] 3214 1 T2 1 T5 1 T39 2
valid_sources[0x15] 2914 1 T3 1 T49 1 T109 89
valid_sources[0x16] 3697 1 T2 1 T137 1 T109 79
valid_sources[0x17] 3085 1 T9 1 T72 1 T22 1
valid_sources[0x18] 2737 1 T5 1 T49 1 T109 108
valid_sources[0x19] 3454 1 T72 4 T138 2 T23 1
valid_sources[0x1a] 3155 1 T3 1 T70 2 T72 1
valid_sources[0x1b] 3934 1 T8 12 T70 1 T22 1
valid_sources[0x1c] 3202 1 T49 1 T71 4 T109 113
valid_sources[0x1d] 2832 1 T12 1 T39 1 T137 1
valid_sources[0x1e] 3349 1 T117 2 T109 107 T24 5
valid_sources[0x1f] 2736 1 T23 1 T109 113 T25 1
valid_sources[0x20] 2667 1 T39 1 T117 1 T137 1
valid_sources[0x21] 2825 1 T23 2 T139 3 T109 85
valid_sources[0x22] 2969 1 T136 1 T109 124 T28 35
valid_sources[0x23] 2646 1 T39 1 T49 1 T137 1
valid_sources[0x24] 3015 1 T3 1 T12 1 T39 1
valid_sources[0x25] 2663 1 T5 2 T12 1 T9 2
valid_sources[0x26] 3090 1 T12 3 T49 1 T72 3
valid_sources[0x27] 2984 1 T109 106 T28 26 T29 7
valid_sources[0x28] 3244 1 T6 112 T39 1 T47 1
valid_sources[0x29] 3604 1 T39 1 T49 1 T47 2
valid_sources[0x2a] 2784 1 T3 1 T5 2 T12 1
valid_sources[0x2b] 2692 1 T49 2 T137 1 T109 100
valid_sources[0x2c] 3218 1 T39 1 T70 1 T140 1
valid_sources[0x2d] 2928 1 T12 2 T13 6 T48 1
valid_sources[0x2e] 3214 1 T5 3 T49 2 T72 1
valid_sources[0x2f] 3630 1 T12 1 T109 103 T28 29
valid_sources[0x30] 2791 1 T39 1 T44 1 T109 114
valid_sources[0x31] 4491 1 T9 1 T44 4 T109 101
valid_sources[0x32] 2736 1 T117 2 T141 1 T109 143
valid_sources[0x33] 3264 1 T5 2 T72 2 T109 117
valid_sources[0x34] 3313 1 T141 2 T109 117 T28 27
valid_sources[0x35] 2535 1 T2 1 T12 1 T9 1
valid_sources[0x36] 3100 1 T49 2 T109 116 T28 22
valid_sources[0x37] 3331 1 T47 1 T44 1 T109 96
valid_sources[0x38] 3181 1 T71 1 T22 1 T23 1
valid_sources[0x39] 2570 1 T12 1 T49 2 T9 1
valid_sources[0x3a] 3195 1 T71 1 T23 2 T109 109
valid_sources[0x3b] 2791 1 T3 5 T137 1 T109 90
valid_sources[0x3c] 3178 1 T3 2 T12 1 T71 5
valid_sources[0x3d] 2742 1 T9 2 T117 2 T109 120
valid_sources[0x3e] 2803 1 T39 1 T49 2 T117 1
valid_sources[0x3f] 3515 1 T5 2 T12 4 T49 1
valid_sources[0x40] 4389 1 T3 5 T8 3 T39 1
valid_sources[0x41] 2878 1 T3 2 T39 1 T70 1
valid_sources[0x42] 2611 1 T3 3 T117 1 T109 125
valid_sources[0x43] 2679 1 T3 2 T72 3 T109 101
valid_sources[0x44] 3963 1 T12 1 T39 1 T49 2
valid_sources[0x45] 3439 1 T12 2 T117 1 T137 1
valid_sources[0x46] 3382 1 T22 1 T109 136 T25 1
valid_sources[0x47] 3400 1 T39 1 T49 1 T9 1
valid_sources[0x48] 2911 1 T5 6 T12 1 T70 1
valid_sources[0x49] 2924 1 T2 1 T12 1 T39 1
valid_sources[0x4a] 3717 1 T49 1 T117 1 T137 1
valid_sources[0x4b] 2955 1 T9 2 T23 7 T44 1
valid_sources[0x4c] 2914 1 T39 1 T109 91 T28 32
valid_sources[0x4d] 3186 1 T12 1 T49 2 T70 1
valid_sources[0x4e] 3751 1 T5 6 T39 2 T23 2
valid_sources[0x4f] 3459 1 T12 1 T109 101 T28 15
valid_sources[0x50] 2815 1 T60 9 T49 1 T70 1
valid_sources[0x51] 3209 1 T9 1 T117 3 T109 107
valid_sources[0x52] 2415 1 T109 89 T28 22 T29 19
valid_sources[0x53] 2693 1 T2 1 T9 1 T140 1
valid_sources[0x54] 3239 1 T22 1 T109 110 T28 31
valid_sources[0x55] 4585 1 T2 1 T12 1 T49 1
valid_sources[0x56] 2691 1 T109 111 T28 12 T29 24
valid_sources[0x57] 3058 1 T70 1 T23 1 T142 1
valid_sources[0x58] 3007 1 T2 1 T117 1 T141 5
valid_sources[0x59] 3718 1 T3 1 T49 1 T109 119
valid_sources[0x5a] 3101 1 T49 1 T22 1 T23 1
valid_sources[0x5b] 3083 1 T8 3 T117 1 T109 136
valid_sources[0x5c] 3180 1 T3 2 T12 1 T49 1
valid_sources[0x5d] 3393 1 T5 2 T8 2 T44 1
valid_sources[0x5e] 3737 1 T2 1 T3 3 T12 1
valid_sources[0x5f] 2809 1 T2 1 T12 1 T49 1
valid_sources[0x60] 2359 1 T70 1 T117 1 T109 121
valid_sources[0x61] 3115 1 T12 1 T39 1 T9 2
valid_sources[0x62] 2964 1 T9 1 T70 1 T48 1
valid_sources[0x63] 3234 1 T49 3 T23 4 T44 1
valid_sources[0x64] 2890 1 T12 1 T117 2 T137 1
valid_sources[0x65] 3440 1 T48 2 T137 1 T46 1
valid_sources[0x66] 3069 1 T9 1 T117 1 T109 105
valid_sources[0x67] 3068 1 T12 1 T9 1 T70 1
valid_sources[0x68] 2929 1 T72 5 T109 81 T28 22
valid_sources[0x69] 3340 1 T12 1 T8 1 T39 1
valid_sources[0x6a] 2716 1 T2 1 T5 2 T72 2
valid_sources[0x6b] 2477 1 T12 1 T39 1 T49 2
valid_sources[0x6c] 2868 1 T3 1 T39 2 T49 1
valid_sources[0x6d] 2686 1 T39 1 T49 1 T9 1
valid_sources[0x6e] 2456 1 T12 3 T39 1 T109 102
valid_sources[0x6f] 3022 1 T2 2 T12 2 T44 1
valid_sources[0x70] 2842 1 T136 1 T109 123 T25 1
valid_sources[0x71] 2541 1 T2 1 T5 2 T109 109
valid_sources[0x72] 3419 1 T12 1 T39 1 T49 1
valid_sources[0x73] 3500 1 T2 1 T9 1 T23 1
valid_sources[0x74] 2885 1 T39 2 T22 1 T117 3
valid_sources[0x75] 3299 1 T72 1 T137 1 T109 112
valid_sources[0x76] 3481 1 T137 1 T109 117 T25 1
valid_sources[0x77] 3752 1 T3 7 T12 1 T137 1
valid_sources[0x78] 2953 1 T39 1 T70 1 T48 1
valid_sources[0x79] 3275 1 T12 2 T39 1 T72 4
valid_sources[0x7a] 2492 1 T5 3 T39 1 T23 2
valid_sources[0x7b] 3132 1 T3 1 T39 1 T47 1
valid_sources[0x7c] 3636 1 T12 1 T23 1 T109 105
valid_sources[0x7d] 3507 1 T39 1 T136 2 T109 99
valid_sources[0x7e] 3080 1 T2 1 T39 1 T117 3
valid_sources[0x7f] 3502 1 T12 1 T49 1 T70 2
valid_sources[0x80] 3101 1 T70 1 T22 1 T44 5



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 284333 1 T2 2 T3 80 T6 21
values[0x0] all_enables biggest_size 144651 1 T2 6 T5 14 T6 22
values[0x1] all_enables biggest_size 144564 1 T2 4 T5 8 T6 14


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4268 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 17545 1 T4 1 T20 1 T21 5



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 7892 1 T27 110 T24 8 T25 99
values[0x0] 6812 1 T4 2 T20 3 T21 4
values[0x1] 7109 1 T4 6 T20 6 T21 7



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3297 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 18516 1 T4 2 T20 4 T21 7



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 102 1 T27 1 T25 16 T65 9
valid_sources[0x01] 75 1 T27 3 T59 6 T65 8
valid_sources[0x02] 77 1 T28 1 T59 2 T65 6
valid_sources[0x03] 77 1 T27 2 T59 1 T65 4
valid_sources[0x04] 100 1 T20 3 T143 1 T27 1
valid_sources[0x05] 61 1 T27 3 T26 5 T59 3
valid_sources[0x06] 59 1 T32 1 T144 1 T145 1
valid_sources[0x07] 76 1 T146 1 T27 2 T26 4
valid_sources[0x08] 50 1 T147 1 T27 1 T28 1
valid_sources[0x09] 66 1 T28 1 T59 1 T65 5
valid_sources[0x0a] 99 1 T27 3 T26 1 T59 2
valid_sources[0x0b] 103 1 T148 1 T65 5 T73 2
valid_sources[0x0c] 84 1 T27 4 T59 4 T65 7
valid_sources[0x0d] 115 1 T26 5 T59 5 T65 2
valid_sources[0x0e] 97 1 T149 1 T147 2 T150 1
valid_sources[0x0f] 87 1 T145 1 T27 3 T25 9
valid_sources[0x10] 122 1 T27 2 T28 1 T26 1
valid_sources[0x11] 46 1 T27 1 T26 2 T59 1
valid_sources[0x12] 73 1 T151 2 T26 1 T59 1
valid_sources[0x13] 77 1 T152 1 T27 6 T26 2
valid_sources[0x14] 71 1 T27 3 T28 1 T29 6
valid_sources[0x15] 86 1 T153 1 T59 1 T65 2
valid_sources[0x16] 41 1 T153 1 T59 2 T65 3
valid_sources[0x17] 60 1 T145 1 T27 1 T26 2
valid_sources[0x18] 56 1 T28 1 T26 2 T59 3
valid_sources[0x19] 82 1 T27 2 T26 2 T65 2
valid_sources[0x1a] 89 1 T28 1 T59 1 T73 1
valid_sources[0x1b] 227 1 T31 1 T32 3 T154 2
valid_sources[0x1c] 89 1 T155 2 T156 2 T27 5
valid_sources[0x1d] 51 1 T27 2 T26 1 T59 3
valid_sources[0x1e] 139 1 T27 2 T24 1 T25 47
valid_sources[0x1f] 71 1 T157 2 T27 3 T26 1
valid_sources[0x20] 103 1 T158 1 T27 4 T26 6
valid_sources[0x21] 55 1 T26 2 T114 3 T124 1
valid_sources[0x22] 66 1 T27 2 T59 1 T65 4
valid_sources[0x23] 51 1 T144 1 T59 2 T75 1
valid_sources[0x24] 63 1 T153 2 T26 1 T59 3
valid_sources[0x25] 67 1 T27 1 T26 1 T59 1
valid_sources[0x26] 53 1 T159 1 T27 1 T30 1
valid_sources[0x27] 78 1 T27 1 T30 1 T26 1
valid_sources[0x28] 52 1 T54 2 T27 1 T26 4
valid_sources[0x29] 66 1 T160 3 T27 2 T26 1
valid_sources[0x2a] 95 1 T160 2 T27 3 T28 3
valid_sources[0x2b] 52 1 T27 5 T26 1 T59 1
valid_sources[0x2c] 115 1 T31 1 T27 2 T24 3
valid_sources[0x2d] 70 1 T29 2 T26 2 T59 2
valid_sources[0x2e] 63 1 T161 1 T27 4 T29 2
valid_sources[0x2f] 68 1 T162 1 T26 4 T59 3
valid_sources[0x30] 94 1 T31 1 T163 1 T160 3
valid_sources[0x31] 161 1 T109 1 T27 10 T28 1
valid_sources[0x32] 53 1 T156 4 T59 4 T66 2
valid_sources[0x33] 103 1 T161 1 T154 1 T27 2
valid_sources[0x34] 66 1 T61 1 T164 1 T158 1
valid_sources[0x35] 78 1 T152 1 T27 3 T59 1
valid_sources[0x36] 56 1 T165 1 T59 2 T65 3
valid_sources[0x37] 50 1 T32 1 T26 1 T59 3
valid_sources[0x38] 697 1 T27 6 T29 2 T26 1
valid_sources[0x39] 57 1 T27 2 T65 1 T75 1
valid_sources[0x3a] 57 1 T24 2 T28 1 T26 1
valid_sources[0x3b] 77 1 T27 3 T59 3 T65 1
valid_sources[0x3c] 83 1 T31 1 T166 5 T27 1
valid_sources[0x3d] 67 1 T144 1 T167 1 T147 4
valid_sources[0x3e] 78 1 T27 3 T28 1 T26 1
valid_sources[0x3f] 155 1 T145 2 T152 1 T27 8
valid_sources[0x40] 65 1 T168 1 T161 1 T27 1
valid_sources[0x41] 57 1 T29 4 T26 2 T59 5
valid_sources[0x42] 100 1 T163 1 T161 1 T27 4
valid_sources[0x43] 74 1 T167 1 T154 1 T27 3
valid_sources[0x44] 48 1 T26 2 T59 2 T65 1
valid_sources[0x45] 51 1 T27 1 T26 2 T59 1
valid_sources[0x46] 74 1 T28 1 T26 1 T59 2
valid_sources[0x47] 41 1 T169 1 T26 2 T59 3
valid_sources[0x48] 64 1 T27 10 T26 1 T59 1
valid_sources[0x49] 54 1 T162 1 T59 4 T66 2
valid_sources[0x4a] 100 1 T32 2 T170 11 T59 4
valid_sources[0x4b] 129 1 T149 1 T27 2 T28 1
valid_sources[0x4c] 55 1 T27 2 T59 1 T65 8
valid_sources[0x4d] 61 1 T59 3 T65 2 T81 1
valid_sources[0x4e] 57 1 T26 1 T59 4 T65 3
valid_sources[0x4f] 863 1 T27 1 T59 8 T65 7
valid_sources[0x50] 89 1 T109 1 T26 1 T59 2
valid_sources[0x51] 70 1 T165 1 T27 3 T26 2
valid_sources[0x52] 57 1 T27 2 T28 1 T26 1
valid_sources[0x53] 84 1 T163 1 T171 4 T65 4
valid_sources[0x54] 70 1 T27 2 T28 1 T26 2
valid_sources[0x55] 49 1 T168 6 T27 2 T59 3
valid_sources[0x56] 29 1 T27 1 T59 1 T65 1
valid_sources[0x57] 60 1 T27 2 T28 1 T59 4
valid_sources[0x58] 95 1 T143 1 T27 2 T28 1
valid_sources[0x59] 63 1 T161 1 T27 2 T65 1
valid_sources[0x5a] 179 1 T61 1 T163 1 T27 4
valid_sources[0x5b] 47 1 T172 1 T27 1 T26 2
valid_sources[0x5c] 73 1 T26 2 T59 1 T65 2
valid_sources[0x5d] 51 1 T26 1 T59 2 T65 1
valid_sources[0x5e] 86 1 T156 1 T161 1 T27 2
valid_sources[0x5f] 78 1 T59 1 T65 5 T73 1
valid_sources[0x60] 55 1 T31 7 T145 1 T155 2
valid_sources[0x61] 77 1 T30 3 T26 1 T59 4
valid_sources[0x62] 87 1 T27 2 T30 1 T26 3
valid_sources[0x63] 67 1 T27 2 T28 2 T59 4
valid_sources[0x64] 45 1 T59 3 T67 1 T173 2
valid_sources[0x65] 57 1 T27 3 T67 3 T111 2
valid_sources[0x66] 64 1 T20 1 T163 1 T167 2
valid_sources[0x67] 59 1 T174 1 T161 1 T26 2
valid_sources[0x68] 70 1 T161 1 T27 1 T59 2
valid_sources[0x69] 72 1 T145 1 T27 3 T26 2
valid_sources[0x6a] 81 1 T26 1 T59 3 T66 2
valid_sources[0x6b] 48 1 T27 3 T28 1 T26 4
valid_sources[0x6c] 68 1 T59 2 T65 6 T111 2
valid_sources[0x6d] 46 1 T146 1 T28 1 T26 2
valid_sources[0x6e] 66 1 T27 2 T28 1 T59 1
valid_sources[0x6f] 74 1 T27 3 T28 2 T26 1
valid_sources[0x70] 69 1 T145 1 T27 2 T65 3
valid_sources[0x71] 95 1 T21 11 T27 2 T26 2
valid_sources[0x72] 86 1 T175 1 T27 1 T26 1
valid_sources[0x73] 63 1 T27 2 T26 3 T59 6
valid_sources[0x74] 80 1 T31 2 T32 3 T27 3
valid_sources[0x75] 60 1 T161 1 T27 4 T59 2
valid_sources[0x76] 134 1 T27 5 T26 3 T59 1
valid_sources[0x77] 38 1 T20 2 T161 1 T27 1
valid_sources[0x78] 83 1 T28 1 T26 3 T65 1
valid_sources[0x79] 56 1 T143 1 T27 1 T26 3
valid_sources[0x7a] 50 1 T26 2 T59 1 T65 1
valid_sources[0x7b] 123 1 T146 1 T152 3 T27 1
valid_sources[0x7c] 78 1 T153 1 T27 2 T26 3
valid_sources[0x7d] 72 1 T164 1 T158 1 T27 4
valid_sources[0x7e] 76 1 T32 1 T147 5 T27 2
valid_sources[0x7f] 67 1 T153 1 T167 1 T169 1
valid_sources[0x80] 123 1 T27 2 T28 1 T26 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 5616 1 T27 103 T24 2 T25 98
values[0x0] all_enables biggest_size 6014 1 T20 1 T21 2 T31 2
values[0x1] all_enables biggest_size 5915 1 T4 1 T21 3 T31 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%