Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.45	90.91	63.83	87.88		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	51766601	12167	0	0
late_debug_enable_rd_A	51766601	2669	0	0
late_debug_enable_regwen_rd_A	51766601	3046	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51766601	12167	0	0
T24	2834	165	0	0
T25	636780	185	0	0
T26	460969	84	0	0
T27	18884	743	0	0
T59	733814	203	0	0
T65	21784	399	0	0
T66	3011	393	0	0
T67	4639	255	0	0
T68	101740	6	0	0
T69	23937	50	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51766601	2669	0	0
T27	18884	58	0	0
T29	53874	7	0	0
T68	101740	21	0	0
T69	23937	47	0	0
T74	4895	4	0	0
T76	487963	280	0	0
T80	108457	90	0	0
T81	60800	30	0	0
T111	9403	40	0	0
T112	56955	11	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51766601	3046	0	0
T27	18884	86	0	0
T29	53874	51	0	0
T68	101740	12	0	0
T69	23937	65	0	0
T74	4895	4	0	0
T76	487963	281	0	0
T80	108457	97	0	0
T81	60800	33	0	0
T111	9403	92	0	0
T112	56955	25	0	0