Module Definition
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Module : prim_mubi8_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.45 90.91 63.83 87.88 57.14 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[7].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[7].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[7].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[7].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_mubi8_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 4 4


Assert Coverage for Module : prim_mubi8_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 174 174 0 0
OutputsKnown_A 27166183 27116770 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 27166183 27114556 0 522


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 174 174 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T12 1 1 0 0
T14 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 27166183 27116770 0 0
T1 523888 523253 0 0
T2 178651 178319 0 0
T3 1604 1553 0 0
T4 1945 1855 0 0
T5 180808 180559 0 0
T6 171170 170942 0 0
T7 307026 306966 0 0
T12 309978 309727 0 0
T14 11378 11296 0 0
T20 2975 2915 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 27166183 27114556 0 522
T1 523888 523226 0 3
T2 178651 178304 0 3
T3 1604 1550 0 3
T4 1945 1852 0 3
T5 180808 180547 0 3
T6 171170 170930 0 3
T7 307026 306963 0 3
T12 309978 309715 0 3
T14 11378 11293 0 3
T20 2975 2912 0 3

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