Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	239426	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	604179	1		T4	16		T37	80		T5	31

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	549372	1		T4	18		T37	80		T20	20
values[0x0]	145213	1		T4	15		T5	37		T7	10
values[0x1]	149020	1		T4	23		T5	54		T7	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	181693	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	661912	1		T4	21		T37	80		T5	39

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3038	1		T53	2		T40	2		T41	19
valid_sources[0x01]	3067	1		T53	2		T54	2		T22	2
valid_sources[0x02]	2954	1		T53	1		T54	1		T41	31
valid_sources[0x03]	3504	1		T4	1		T22	1		T41	19
valid_sources[0x04]	3189	1		T17	1		T54	1		T22	1
valid_sources[0x05]	2930	1		T22	2		T40	1		T41	27
valid_sources[0x06]	3214	1		T17	1		T41	24		T82	18
valid_sources[0x07]	4432	1		T17	1		T22	1		T40	3
valid_sources[0x08]	2880	1		T53	1		T54	1		T40	2
valid_sources[0x09]	3036	1		T4	3		T53	1		T54	1
valid_sources[0x0a]	3157	1		T17	1		T54	1		T22	1
valid_sources[0x0b]	3552	1		T54	1		T42	1		T41	17
valid_sources[0x0c]	3771	1		T22	2		T40	7		T41	17
valid_sources[0x0d]	3494	1		T54	1		T140	1		T40	2
valid_sources[0x0e]	3024	1		T54	1		T40	5		T41	20
valid_sources[0x0f]	3016	1		T6	1		T54	1		T42	1
valid_sources[0x10]	3322	1		T53	3		T22	1		T40	4
valid_sources[0x11]	3128	1		T56	1		T53	1		T39	145
valid_sources[0x12]	2824	1		T17	1		T53	1		T42	1
valid_sources[0x13]	2837	1		T54	2		T22	1		T58	3
valid_sources[0x14]	3393	1		T56	1		T58	3		T140	2
valid_sources[0x15]	3426	1		T54	1		T40	3		T41	20
valid_sources[0x16]	3697	1		T4	1		T42	2		T40	8
valid_sources[0x17]	3309	1		T58	3		T40	4		T41	19
valid_sources[0x18]	3134	1		T53	1		T40	4		T41	23
valid_sources[0x19]	3242	1		T53	1		T22	1		T40	2
valid_sources[0x1a]	3099	1		T22	1		T58	1		T40	3
valid_sources[0x1b]	2808	1		T4	4		T56	1		T22	1
valid_sources[0x1c]	3317	1		T17	1		T54	1		T39	36
valid_sources[0x1d]	3460	1		T22	4		T40	1		T41	27
valid_sources[0x1e]	3794	1		T7	1		T17	1		T53	3
valid_sources[0x1f]	3552	1		T21	4		T53	2		T40	1
valid_sources[0x20]	3452	1		T54	1		T40	2		T41	26
valid_sources[0x21]	3796	1		T17	1		T54	1		T40	2
valid_sources[0x22]	3013	1		T17	1		T52	2		T53	1
valid_sources[0x23]	2769	1		T140	2		T40	4		T41	23
valid_sources[0x24]	3093	1		T21	6		T53	1		T22	1
valid_sources[0x25]	3055	1		T4	1		T37	80		T53	1
valid_sources[0x26]	3311	1		T17	1		T53	1		T40	1
valid_sources[0x27]	3454	1		T4	1		T42	1		T40	3
valid_sources[0x28]	3380	1		T40	8		T41	17		T82	10
valid_sources[0x29]	3141	1		T40	3		T41	17		T73	18
valid_sources[0x2a]	2761	1		T53	1		T22	1		T58	3
valid_sources[0x2b]	3661	1		T4	1		T40	3		T41	31
valid_sources[0x2c]	2901	1		T54	2		T22	2		T41	20
valid_sources[0x2d]	3003	1		T52	4		T22	1		T58	1
valid_sources[0x2e]	3085	1		T56	1		T53	1		T58	2
valid_sources[0x2f]	2969	1		T4	1		T54	1		T22	1
valid_sources[0x30]	3117	1		T56	1		T40	4		T41	17
valid_sources[0x31]	3137	1		T53	1		T22	1		T40	3
valid_sources[0x32]	3374	1		T17	1		T54	1		T40	3
valid_sources[0x33]	2920	1		T11	3		T54	1		T22	3
valid_sources[0x34]	3334	1		T22	4		T42	2		T40	1
valid_sources[0x35]	2763	1		T42	1		T40	3		T41	25
valid_sources[0x36]	3872	1		T53	1		T54	2		T22	2
valid_sources[0x37]	3152	1		T4	3		T40	3		T41	18
valid_sources[0x38]	3583	1		T14	6		T40	7		T41	25
valid_sources[0x39]	3422	1		T53	1		T42	1		T40	3
valid_sources[0x3a]	3103	1		T40	3		T41	28		T73	12
valid_sources[0x3b]	3620	1		T22	1		T39	449		T42	1
valid_sources[0x3c]	3179	1		T22	1		T40	1		T41	26
valid_sources[0x3d]	3331	1		T40	2		T41	26		T82	47
valid_sources[0x3e]	4160	1		T56	1		T53	1		T22	1
valid_sources[0x3f]	2887	1		T56	1		T22	1		T40	1
valid_sources[0x40]	2971	1		T17	1		T22	2		T40	4
valid_sources[0x41]	2716	1		T17	1		T22	1		T42	4
valid_sources[0x42]	2743	1		T28	1		T40	6		T41	26
valid_sources[0x43]	3034	1		T53	2		T40	6		T41	25
valid_sources[0x44]	2928	1		T22	2		T40	2		T41	14
valid_sources[0x45]	3266	1		T54	1		T22	2		T140	1
valid_sources[0x46]	3576	1		T17	1		T40	3		T41	17
valid_sources[0x47]	3393	1		T22	1		T57	9		T40	3
valid_sources[0x48]	2901	1		T22	1		T42	1		T40	3
valid_sources[0x49]	3350	1		T42	1		T40	4		T41	24
valid_sources[0x4a]	3252	1		T7	2		T22	1		T42	1
valid_sources[0x4b]	3934	1		T54	3		T42	1		T40	1
valid_sources[0x4c]	3263	1		T17	1		T40	5		T41	21
valid_sources[0x4d]	3123	1		T53	2		T22	1		T42	1
valid_sources[0x4e]	3008	1		T54	2		T40	2		T41	22
valid_sources[0x4f]	3589	1		T17	1		T141	2		T42	2
valid_sources[0x50]	2770	1		T140	2		T40	2		T41	28
valid_sources[0x51]	3066	1		T53	1		T42	1		T40	2
valid_sources[0x52]	3047	1		T4	1		T17	2		T21	1
valid_sources[0x53]	3111	1		T42	1		T41	19		T82	2
valid_sources[0x54]	3137	1		T42	2		T40	2		T41	22
valid_sources[0x55]	4838	1		T53	3		T22	1		T140	1
valid_sources[0x56]	2864	1		T42	1		T40	5		T41	25
valid_sources[0x57]	3134	1		T4	1		T42	1		T40	3
valid_sources[0x58]	3826	1		T140	1		T42	1		T40	5
valid_sources[0x59]	3259	1		T140	1		T40	3		T41	17
valid_sources[0x5a]	3350	1		T4	2		T20	40		T52	1
valid_sources[0x5b]	3310	1		T58	1		T40	3		T41	18
valid_sources[0x5c]	3537	1		T7	6		T21	3		T42	3
valid_sources[0x5d]	3099	1		T53	1		T42	1		T40	4
valid_sources[0x5e]	3400	1		T54	1		T22	1		T40	2
valid_sources[0x5f]	3633	1		T22	1		T42	1		T40	1
valid_sources[0x60]	3258	1		T41	32		T82	9		T73	15
valid_sources[0x61]	3352	1		T54	3		T42	1		T40	5
valid_sources[0x62]	2955	1		T21	2		T22	1		T40	2
valid_sources[0x63]	3258	1		T6	3		T140	1		T40	4
valid_sources[0x64]	3252	1		T17	1		T140	1		T42	1
valid_sources[0x65]	3345	1		T17	1		T142	1		T22	1
valid_sources[0x66]	2866	1		T140	1		T40	2		T41	18
valid_sources[0x67]	2872	1		T22	1		T42	2		T41	19
valid_sources[0x68]	3258	1		T6	3		T54	1		T40	3
valid_sources[0x69]	3537	1		T52	3		T22	1		T140	3
valid_sources[0x6a]	3041	1		T40	3		T41	29		T82	10
valid_sources[0x6b]	3722	1		T53	2		T22	1		T41	21
valid_sources[0x6c]	3760	1		T40	2		T41	19		T73	26
valid_sources[0x6d]	3169	1		T6	2		T22	2		T40	3
valid_sources[0x6e]	3671	1		T42	1		T40	1		T41	15
valid_sources[0x6f]	3628	1		T54	1		T42	2		T40	2
valid_sources[0x70]	3529	1		T22	1		T40	2		T41	19
valid_sources[0x71]	2931	1		T42	2		T40	5		T41	29
valid_sources[0x72]	3539	1		T53	1		T54	1		T22	1
valid_sources[0x73]	3802	1		T42	1		T40	1		T41	20
valid_sources[0x74]	3276	1		T52	2		T42	1		T40	3
valid_sources[0x75]	2974	1		T54	1		T40	3		T41	26
valid_sources[0x76]	3551	1		T4	1		T56	1		T42	1
valid_sources[0x77]	3459	1		T22	1		T42	1		T40	3
valid_sources[0x78]	3179	1		T4	1		T53	1		T54	2
valid_sources[0x79]	3728	1		T4	2		T22	1		T40	2
valid_sources[0x7a]	3581	1		T42	1		T40	1		T41	31
valid_sources[0x7b]	3422	1		T71	4		T56	1		T54	1
valid_sources[0x7c]	3338	1		T17	1		T22	1		T39	135
valid_sources[0x7d]	3484	1		T40	1		T41	17		T82	19
valid_sources[0x7e]	2829	1		T22	1		T40	1		T41	19
valid_sources[0x7f]	3358	1		T53	1		T22	1		T42	1
valid_sources[0x80]	4162	1		T17	2		T53	1		T42	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

318650

1

T4

7

T37

80

T20

13

values[0x0]

all_enables

biggest_size

143388

1

T4

5

T5

20

T7

3

values[0x1]

all_enables

biggest_size

142141

1

T4

4

T5

11

T7

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5809	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	19713	1		T31	10		T33	1		T35	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	11100	1		T39	51		T42	68		T40	243
values[0x0]	7060	1		T31	13		T33	4		T35	4
values[0x1]	7362	1		T31	9		T32	1		T33	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4401	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	21121	1		T31	12		T33	1		T35	3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57	1		T143	1		T40	5		T76	1
valid_sources[0x01]	49	1		T144	1		T40	5		T88	2
valid_sources[0x02]	61	1		T31	1		T143	1		T88	6
valid_sources[0x03]	76	1		T44	3		T42	1		T88	3
valid_sources[0x04]	120	1		T68	4		T42	1		T40	3
valid_sources[0x05]	77	1		T42	1		T40	5		T88	3
valid_sources[0x06]	124	1		T42	1		T40	5		T75	2
valid_sources[0x07]	52	1		T145	1		T40	4		T88	1
valid_sources[0x08]	90	1		T121	1		T42	1		T88	2
valid_sources[0x09]	58	1		T40	3		T75	3		T88	1
valid_sources[0x0a]	50	1		T42	3		T40	5		T88	5
valid_sources[0x0b]	106	1		T146	2		T39	36		T42	6
valid_sources[0x0c]	88	1		T147	1		T42	1		T88	7
valid_sources[0x0d]	90	1		T145	1		T42	1		T40	4
valid_sources[0x0e]	82	1		T74	2		T88	2		T78	7
valid_sources[0x0f]	80	1		T148	6		T42	1		T40	10
valid_sources[0x10]	75	1		T42	1		T40	10		T88	2
valid_sources[0x11]	121	1		T121	2		T149	1		T42	1
valid_sources[0x12]	71	1		T42	1		T40	4		T75	1
valid_sources[0x13]	148	1		T42	2		T40	1		T75	1
valid_sources[0x14]	101	1		T150	1		T151	1		T152	15
valid_sources[0x15]	91	1		T153	2		T75	10		T88	2
valid_sources[0x16]	98	1		T39	5		T40	10		T75	2
valid_sources[0x17]	79	1		T80	4		T42	2		T40	3
valid_sources[0x18]	88	1		T68	6		T145	1		T42	1
valid_sources[0x19]	145	1		T154	12		T74	1		T88	4
valid_sources[0x1a]	87	1		T155	4		T42	1		T40	16
valid_sources[0x1b]	75	1		T42	1		T40	2		T88	6
valid_sources[0x1c]	58	1		T40	2		T75	2		T88	2
valid_sources[0x1d]	90	1		T144	1		T40	3		T88	2
valid_sources[0x1e]	108	1		T42	3		T75	1		T76	1
valid_sources[0x1f]	61	1		T156	3		T145	1		T39	1
valid_sources[0x20]	201	1		T42	2		T40	2		T88	1
valid_sources[0x21]	150	1		T42	1		T40	13		T81	3
valid_sources[0x22]	80	1		T149	2		T42	1		T40	8
valid_sources[0x23]	121	1		T150	1		T157	1		T42	3
valid_sources[0x24]	81	1		T158	14		T42	1		T40	2
valid_sources[0x25]	62	1		T40	3		T76	1		T88	1
valid_sources[0x26]	62	1		T150	1		T40	5		T75	1
valid_sources[0x27]	83	1		T153	2		T42	2		T40	1
valid_sources[0x28]	879	1		T31	1		T42	2		T40	9
valid_sources[0x29]	85	1		T31	2		T159	1		T160	3
valid_sources[0x2a]	127	1		T40	1		T75	1		T88	2
valid_sources[0x2b]	67	1		T42	1		T40	4		T88	1
valid_sources[0x2c]	104	1		T42	1		T40	2		T74	2
valid_sources[0x2d]	74	1		T80	1		T42	1		T40	2
valid_sources[0x2e]	48	1		T31	1		T40	2		T76	1
valid_sources[0x2f]	57	1		T40	1		T88	3		T79	1
valid_sources[0x30]	155	1		T161	18		T42	3		T40	4
valid_sources[0x31]	73	1		T40	2		T87	5		T88	3
valid_sources[0x32]	84	1		T42	2		T40	3		T82	2
valid_sources[0x33]	315	1		T39	15		T40	3		T74	1
valid_sources[0x34]	79	1		T156	7		T42	2		T40	9
valid_sources[0x35]	206	1		T42	2		T76	2		T88	1
valid_sources[0x36]	89	1		T42	1		T40	7		T86	2
valid_sources[0x37]	146	1		T162	1		T40	2		T76	1
valid_sources[0x38]	129	1		T40	2		T75	2		T88	1
valid_sources[0x39]	89	1		T42	1		T40	17		T88	2
valid_sources[0x3a]	84	1		T40	2		T82	1		T74	1
valid_sources[0x3b]	94	1		T144	1		T40	9		T88	7
valid_sources[0x3c]	85	1		T157	1		T42	1		T40	3
valid_sources[0x3d]	116	1		T147	1		T42	1		T40	3
valid_sources[0x3e]	79	1		T145	1		T42	1		T40	4
valid_sources[0x3f]	115	1		T40	2		T73	1		T83	1
valid_sources[0x40]	83	1		T163	1		T42	3		T40	1
valid_sources[0x41]	66	1		T40	3		T75	3		T88	6
valid_sources[0x42]	92	1		T153	1		T164	2		T42	1
valid_sources[0x43]	73	1		T40	8		T73	3		T75	4
valid_sources[0x44]	97	1		T146	1		T40	11		T74	1
valid_sources[0x45]	85	1		T44	1		T165	6		T42	1
valid_sources[0x46]	80	1		T42	1		T40	3		T88	3
valid_sources[0x47]	82	1		T166	3		T167	5		T42	4
valid_sources[0x48]	58	1		T42	1		T40	5		T75	1
valid_sources[0x49]	48	1		T42	1		T88	3		T79	1
valid_sources[0x4a]	85	1		T42	3		T86	1		T78	1
valid_sources[0x4b]	104	1		T149	1		T145	1		T42	3
valid_sources[0x4c]	141	1		T121	1		T168	10		T147	1
valid_sources[0x4d]	54	1		T42	1		T40	4		T82	1
valid_sources[0x4e]	86	1		T166	1		T40	2		T88	2
valid_sources[0x4f]	74	1		T42	3		T40	4		T75	1
valid_sources[0x50]	102	1		T42	2		T40	6		T76	1
valid_sources[0x51]	68	1		T33	10		T40	1		T88	5
valid_sources[0x52]	94	1		T149	1		T42	1		T40	3
valid_sources[0x53]	57	1		T31	1		T42	2		T40	5
valid_sources[0x54]	77	1		T88	3		T79	3		T92	7
valid_sources[0x55]	63	1		T42	2		T40	1		T74	2
valid_sources[0x56]	76	1		T42	2		T40	8		T75	1
valid_sources[0x57]	62	1		T31	2		T163	1		T40	2
valid_sources[0x58]	146	1		T42	2		T40	3		T81	3
valid_sources[0x59]	65	1		T42	2		T40	1		T88	6
valid_sources[0x5a]	97	1		T40	24		T41	2		T88	2
valid_sources[0x5b]	68	1		T153	2		T42	1		T40	2
valid_sources[0x5c]	79	1		T42	1		T40	3		T75	3
valid_sources[0x5d]	81	1		T42	2		T40	7		T75	1
valid_sources[0x5e]	140	1		T169	2		T42	1		T40	4
valid_sources[0x5f]	89	1		T150	1		T145	1		T40	7
valid_sources[0x60]	108	1		T31	1		T164	1		T126	17
valid_sources[0x61]	69	1		T40	2		T88	2		T79	3
valid_sources[0x62]	70	1		T80	2		T151	1		T40	1
valid_sources[0x63]	75	1		T153	3		T40	2		T76	1
valid_sources[0x64]	63	1		T164	1		T42	1		T40	5
valid_sources[0x65]	100	1		T170	19		T39	3		T40	2
valid_sources[0x66]	117	1		T40	8		T75	2		T88	2
valid_sources[0x67]	98	1		T32	1		T164	1		T75	8
valid_sources[0x68]	72	1		T80	5		T167	9		T171	2
valid_sources[0x69]	64	1		T172	3		T40	1		T82	1
valid_sources[0x6a]	89	1		T40	3		T75	4		T88	4
valid_sources[0x6b]	157	1		T162	1		T39	2		T42	2
valid_sources[0x6c]	70	1		T73	3		T74	2		T88	2
valid_sources[0x6d]	115	1		T43	1		T145	1		T40	2
valid_sources[0x6e]	93	1		T42	1		T40	4		T74	1
valid_sources[0x6f]	61	1		T40	6		T82	2		T88	1
valid_sources[0x70]	133	1		T70	2		T40	1		T82	1
valid_sources[0x71]	272	1		T42	1		T40	1		T75	4
valid_sources[0x72]	72	1		T42	1		T40	6		T88	1
valid_sources[0x73]	61	1		T39	7		T42	3		T40	1
valid_sources[0x74]	57	1		T153	1		T42	1		T40	5
valid_sources[0x75]	58	1		T153	1		T40	8		T88	2
valid_sources[0x76]	107	1		T40	7		T75	6		T88	3
valid_sources[0x77]	78	1		T143	1		T42	1		T40	5
valid_sources[0x78]	75	1		T39	7		T42	1		T40	6
valid_sources[0x79]	66	1		T42	4		T40	1		T88	1
valid_sources[0x7a]	83	1		T40	7		T74	1		T75	5
valid_sources[0x7b]	78	1		T166	2		T40	2		T75	1
valid_sources[0x7c]	69	1		T42	1		T76	1		T88	5
valid_sources[0x7d]	81	1		T42	1		T40	2		T85	2
valid_sources[0x7e]	142	1		T159	1		T42	2		T40	1
valid_sources[0x7f]	68	1		T162	1		T42	2		T40	1
valid_sources[0x80]	71	1		T70	2		T42	3		T40	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7299

1

T39

43

T42

65

T40

239

values[0x0]

all_enables

biggest_size

6245

1

T31

7

T33

1

T67

3

values[0x1]

all_enables

biggest_size

6169

1

T31

3

T35

2

T68

3