Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	276333	1		T4	40		T5	60		T7	14
full_word	605672	1		T4	16		T37	80		T5	31

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	881715	1		T4	56		T37	80		T5	91
auto[TlIntgErrCmd]	107	1		T41	2		T73	2		T91	10
auto[TlIntgErrData]	89	1		T41	5		T73	2		T91	4
auto[TlIntgErrBoth]	94	1		T41	3		T73	6		T91	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	551082	1		T4	18		T37	80		T20	20
auto[1]	330923	1		T4	38		T5	91		T7	18

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	232148	1		T4	11		T20	7		T6	5
auto[TlIntgErrNone]	partial	auto[1]	43925	1		T4	29		T5	60		T7	14
auto[TlIntgErrNone]	full_word	auto[0]	318809	1		T4	7		T37	80		T20	13
auto[TlIntgErrNone]	full_word	auto[1]	286833	1		T4	9		T5	31		T7	4
auto[TlIntgErrCmd]	partial	auto[0]	36	1		T91	4		T122	1		T128	1
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T41	1		T73	1		T91	3
auto[TlIntgErrCmd]	full_word	auto[0]	9	1		T41	1		T73	1		T91	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T91	2		T128	2		T136	1
auto[TlIntgErrData]	partial	auto[0]	29	1		T41	1		T73	2		T91	2
auto[TlIntgErrData]	partial	auto[1]	50	1		T41	3		T91	2		T122	5
auto[TlIntgErrData]	full_word	auto[0]	6	1		T130	1		T135	1		T132	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T41	1		T131	1		T134	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1		T41	1		T73	4		T91	4
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T41	2		T73	2		T91	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T133	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T137	1		T138	1		-	-