Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.45	90.91	63.83	87.88		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	48934982	12402	0	0
late_debug_enable_rd_A	48934982	3784	0	0
late_debug_enable_regwen_rd_A	48934982	3771	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48934982	12402	0	0
T39	112217	39	0	0
T40	701016	377	0	0
T41	38530	2	0	0
T42	3564	194	0	0
T73	54974	2	0	0
T74	7041	17	0	0
T75	125942	163	0	0
T76	58603	35	0	0
T77	80460	22	0	0
T78	283790	36	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48934982	3784	0	0
T39	112217	53	0	0
T41	38530	37	0	0
T74	7041	8	0	0
T77	80460	14	0	0
T79	19025	273	0	0
T81	4652	3	0	0
T82	20770	7	0	0
T84	6169	4	0	0
T85	8647	4	0	0
T117	22224	27	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48934982	3771	0	0
T39	112217	65	0	0
T41	38530	14	0	0
T74	7041	7	0	0
T77	80460	30	0	0
T79	19025	182	0	0
T84	6169	4	0	0
T85	8647	4	0	0
T90	4639	9	0	0
T117	22224	4	0	0
T122	54779	29	0	0