Unified Coverage Report :: Module

Module : tlul_adapter_host

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.tl_adapter_host_sba	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.tl_adapter_host_sba

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.14	100.00	100.00	75.71		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.45	90.91	63.83	87.88		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cmd_intg_gen	100.00	100.00					100.00
u_rsp_chk	93.93	100.00	100.00	75.71			100.00

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : tlul_adapter_host

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
ALWAYS	131	4	4	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
ALWAYS	166	0	0
ALWAYS	176	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
95	1	1
115	1	1
117	1	1
118	1	1
119	1	1
131	1	1
132	1	1
133	1	1
134	1	1
			MISSING_ELSE
140	1	1
144	1	1
148	1	1
152	1	1
166		unreachable
168		unreachable
169		unreachable
170		unreachable
171		unreachable
			==> MISSING_ELSE
176		unreachable
177		unreachable
179		unreachable

Cond Coverage for Module : tlul_adapter_host

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       93
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----

-1-	Status	Tests
0	Covered	T2,T10,T13
1	Covered	T1,T2,T3

 LINE       95
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----

-1-	Status	Tests
0	Covered	T2,T10,T13
1	Covered	T1,T2,T3

 LINE       95
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----

-1-	Status	Tests
0	Covered	T2,T10,T13
1	Covered	T2,T10,T13

 LINE       140
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T10
0	1	Covered	T10,T15,T66
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T15,T16
1	0	Covered	T10,T15,T16

Branch Coverage for Module : tlul_adapter_host

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	93	2	2	100.00
IF	131	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	93	((~we_i)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T10,T13



	LineNo.	Expression
-1-:	131	if ((!rst_ni))
-2-:	133	if (intg_err)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T10,T15,T16
0	0	Covered	T1,T2,T3

Assert Coverage for Module : tlul_adapter_host

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DontExceeedMaxReqs	48934982	86783	0	0

DontExceeedMaxReqs

Name	Attempts	Real Successes
Total	48934982	86783
T2	216788	1097
T3	6904	0
T8	72052	0
T9	18483	0
T10	107629	109
T13	794251	546
T15	0	290
T16	0	62
T34	83777	271
T38	306982	922
T45	21064	424
T48	82456	581
T72	0	151