SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.45 | 90.91 | 63.83 | 87.88 | 57.14 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 163 | 163 | 0 | 0 |
OutputsKnown_A | 26918808 | 26876928 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26918808 | 26876928 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 163 | 163 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T45 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26918808 | 26876928 | 0 | 0 |
T1 | 1410 | 1345 | 0 | 0 |
T2 | 216788 | 216706 | 0 | 0 |
T3 | 6904 | 6142 | 0 | 0 |
T8 | 72052 | 71681 | 0 | 0 |
T9 | 18483 | 18402 | 0 | 0 |
T10 | 107629 | 107531 | 0 | 0 |
T13 | 794251 | 794185 | 0 | 0 |
T34 | 83777 | 83712 | 0 | 0 |
T45 | 21064 | 20998 | 0 | 0 |
T48 | 82456 | 82389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26918808 | 26876928 | 0 | 0 |
T1 | 1410 | 1345 | 0 | 0 |
T2 | 216788 | 216706 | 0 | 0 |
T3 | 6904 | 6142 | 0 | 0 |
T8 | 72052 | 71681 | 0 | 0 |
T9 | 18483 | 18402 | 0 | 0 |
T10 | 107629 | 107531 | 0 | 0 |
T13 | 794251 | 794185 | 0 | 0 |
T34 | 83777 | 83712 | 0 | 0 |
T45 | 21064 | 20998 | 0 | 0 |
T48 | 82456 | 82389 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |