Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	222237	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	628321	1		T1	8		T2	11		T29	80

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	526723	1		T29	80		T30	80		T14	21
values[0x0]	160241	1		T1	26		T2	13		T5	18
values[0x1]	163594	1		T1	13		T2	16		T5	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	170612	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	679946	1		T1	9		T2	12		T29	80

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3563	1		T2	1		T141	1		T57	3
valid_sources[0x01]	3036	1		T2	1		T29	1		T24	1
valid_sources[0x02]	4099	1		T24	1		T57	2		T51	18
valid_sources[0x03]	3554	1		T8	2		T142	1		T141	2
valid_sources[0x04]	2877	1		T141	1		T51	18		T56	33
valid_sources[0x05]	2794	1		T32	1		T57	4		T56	19
valid_sources[0x06]	4150	1		T29	1		T34	2		T57	2
valid_sources[0x07]	2975	1		T29	1		T24	1		T57	5
valid_sources[0x08]	4201	1		T30	6		T57	1		T56	24
valid_sources[0x09]	2964	1		T29	1		T57	2		T56	27
valid_sources[0x0a]	3204	1		T142	9		T141	2		T57	2
valid_sources[0x0b]	3258	1		T5	1		T30	19		T24	1
valid_sources[0x0c]	2676	1		T29	2		T15	2		T24	1
valid_sources[0x0d]	4105	1		T57	5		T56	26		T87	4
valid_sources[0x0e]	3190	1		T2	1		T32	1		T141	1
valid_sources[0x0f]	2954	1		T8	1		T57	2		T56	24
valid_sources[0x10]	2592	1		T141	1		T57	3		T56	20
valid_sources[0x11]	3156	1		T24	1		T142	1		T57	2
valid_sources[0x12]	2937	1		T24	1		T141	1		T57	1
valid_sources[0x13]	3528	1		T141	1		T56	22		T87	4
valid_sources[0x14]	4326	1		T2	1		T32	2		T57	1
valid_sources[0x15]	3317	1		T29	1		T8	1		T141	1
valid_sources[0x16]	2823	1		T24	1		T25	64		T57	3
valid_sources[0x17]	3404	1		T29	2		T15	2		T141	2
valid_sources[0x18]	3107	1		T29	2		T16	1		T57	4
valid_sources[0x19]	3824	1		T57	1		T51	4		T56	26
valid_sources[0x1a]	3113	1		T37	1		T57	1		T51	2
valid_sources[0x1b]	3130	1		T32	1		T57	3		T51	8
valid_sources[0x1c]	3403	1		T29	1		T32	1		T141	1
valid_sources[0x1d]	3347	1		T24	1		T57	4		T56	15
valid_sources[0x1e]	3475	1		T57	3		T51	1		T56	34
valid_sources[0x1f]	3217	1		T29	1		T11	1		T56	20
valid_sources[0x20]	3029	1		T32	1		T57	2		T56	22
valid_sources[0x21]	3175	1		T29	1		T8	1		T24	1
valid_sources[0x22]	2938	1		T29	1		T11	1		T142	1
valid_sources[0x23]	3218	1		T2	1		T57	3		T51	23
valid_sources[0x24]	3146	1		T2	1		T32	1		T57	2
valid_sources[0x25]	3432	1		T141	1		T57	1		T56	16
valid_sources[0x26]	3867	1		T141	1		T57	4		T51	2
valid_sources[0x27]	3545	1		T32	1		T141	1		T57	5
valid_sources[0x28]	3780	1		T1	2		T141	1		T51	36
valid_sources[0x29]	4008	1		T29	2		T141	1		T57	3
valid_sources[0x2a]	3415	1		T37	2		T143	4		T57	1
valid_sources[0x2b]	3220	1		T141	1		T57	3		T51	5
valid_sources[0x2c]	2851	1		T2	1		T11	1		T57	4
valid_sources[0x2d]	3341	1		T24	2		T57	1		T56	34
valid_sources[0x2e]	3267	1		T57	1		T51	4		T56	25
valid_sources[0x2f]	2583	1		T8	3		T56	30		T87	4
valid_sources[0x30]	3456	1		T32	1		T57	1		T56	16
valid_sources[0x31]	4126	1		T24	1		T57	1		T56	27
valid_sources[0x32]	3851	1		T1	1		T29	1		T5	1
valid_sources[0x33]	4150	1		T57	2		T51	8		T56	22
valid_sources[0x34]	3346	1		T141	1		T57	1		T56	20
valid_sources[0x35]	3185	1		T1	1		T15	3		T32	1
valid_sources[0x36]	3475	1		T29	1		T5	1		T32	1
valid_sources[0x37]	2921	1		T57	1		T51	29		T56	26
valid_sources[0x38]	3614	1		T5	1		T57	1		T56	25
valid_sources[0x39]	3609	1		T32	1		T141	1		T56	20
valid_sources[0x3a]	3358	1		T141	1		T57	1		T51	3
valid_sources[0x3b]	3283	1		T5	1		T141	1		T57	2
valid_sources[0x3c]	3041	1		T29	1		T5	1		T57	1
valid_sources[0x3d]	2793	1		T30	2		T141	1		T57	5
valid_sources[0x3e]	3240	1		T32	1		T57	4		T56	19
valid_sources[0x3f]	3782	1		T16	1		T141	1		T57	2
valid_sources[0x40]	3193	1		T1	1		T29	1		T24	1
valid_sources[0x41]	3982	1		T1	2		T33	2		T57	1
valid_sources[0x42]	3372	1		T29	2		T55	140		T51	7
valid_sources[0x43]	3034	1		T1	3		T29	1		T56	24
valid_sources[0x44]	2993	1		T32	1		T57	1		T56	34
valid_sources[0x45]	3225	1		T8	4		T143	6		T57	1
valid_sources[0x46]	3114	1		T57	1		T51	5		T56	23
valid_sources[0x47]	3015	1		T57	3		T56	17		T87	4
valid_sources[0x48]	3300	1		T1	1		T32	1		T141	1
valid_sources[0x49]	3064	1		T51	4		T56	27		T87	7
valid_sources[0x4a]	3083	1		T32	1		T37	3		T57	2
valid_sources[0x4b]	3112	1		T142	9		T141	1		T57	2
valid_sources[0x4c]	3392	1		T32	1		T141	1		T57	2
valid_sources[0x4d]	3675	1		T57	1		T56	22		T87	10
valid_sources[0x4e]	3082	1		T30	1		T57	5		T56	31
valid_sources[0x4f]	5109	1		T17	2		T57	1		T56	22
valid_sources[0x50]	2940	1		T15	2		T57	2		T51	1
valid_sources[0x51]	3696	1		T29	1		T141	1		T57	2
valid_sources[0x52]	4002	1		T32	1		T57	1		T56	31
valid_sources[0x53]	3394	1		T57	1		T56	14		T87	1
valid_sources[0x54]	2852	1		T29	2		T57	3		T51	5
valid_sources[0x55]	3570	1		T5	1		T24	2		T56	35
valid_sources[0x56]	3196	1		T57	3		T56	23		T87	3
valid_sources[0x57]	3040	1		T143	3		T57	1		T56	18
valid_sources[0x58]	3452	1		T57	2		T51	8		T56	28
valid_sources[0x59]	2985	1		T30	2		T32	1		T57	4
valid_sources[0x5a]	3388	1		T2	1		T29	1		T20	2
valid_sources[0x5b]	3061	1		T29	1		T57	5		T56	17
valid_sources[0x5c]	3446	1		T1	2		T24	1		T141	1
valid_sources[0x5d]	3407	1		T142	2		T141	1		T57	5
valid_sources[0x5e]	2340	1		T57	5		T56	19		T87	4
valid_sources[0x5f]	3728	1		T29	2		T34	7		T57	2
valid_sources[0x60]	3252	1		T29	1		T57	3		T51	7
valid_sources[0x61]	3041	1		T57	2		T51	4		T56	17
valid_sources[0x62]	3140	1		T56	30		T87	2		T88	255
valid_sources[0x63]	3126	1		T57	2		T56	12		T87	1
valid_sources[0x64]	2951	1		T17	1		T141	2		T57	5
valid_sources[0x65]	3677	1		T15	2		T32	1		T141	1
valid_sources[0x66]	3420	1		T32	1		T57	2		T56	23
valid_sources[0x67]	2961	1		T141	1		T51	2		T56	21
valid_sources[0x68]	3552	1		T8	3		T32	1		T57	1
valid_sources[0x69]	2884	1		T32	1		T24	1		T141	1
valid_sources[0x6a]	3791	1		T29	1		T5	1		T11	1
valid_sources[0x6b]	3450	1		T29	3		T18	32		T57	5
valid_sources[0x6c]	3243	1		T8	1		T141	1		T57	4
valid_sources[0x6d]	3627	1		T29	2		T55	140		T57	3
valid_sources[0x6e]	3518	1		T1	1		T5	1		T11	1
valid_sources[0x6f]	3745	1		T141	2		T55	554		T57	6
valid_sources[0x70]	3594	1		T29	1		T57	5		T56	13
valid_sources[0x71]	3958	1		T1	1		T2	1		T57	1
valid_sources[0x72]	3083	1		T30	2		T24	1		T57	2
valid_sources[0x73]	3544	1		T2	1		T29	1		T57	1
valid_sources[0x74]	2750	1		T5	1		T32	3		T141	1
valid_sources[0x75]	3120	1		T141	2		T57	2		T56	17
valid_sources[0x76]	3926	1		T5	1		T30	4		T32	2
valid_sources[0x77]	3242	1		T29	1		T15	1		T57	1
valid_sources[0x78]	3151	1		T8	1		T19	39		T57	2
valid_sources[0x79]	3032	1		T5	1		T8	2		T141	1
valid_sources[0x7a]	3466	1		T142	1		T57	2		T51	9
valid_sources[0x7b]	3703	1		T32	1		T141	1		T56	23
valid_sources[0x7c]	3331	1		T2	1		T29	1		T32	1
valid_sources[0x7d]	3034	1		T32	1		T57	4		T56	24
valid_sources[0x7e]	3319	1		T29	1		T32	1		T45	89
valid_sources[0x7f]	2857	1		T1	2		T2	1		T57	2
valid_sources[0x80]	3387	1		T29	1		T30	2		T32	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

312610

1

T29

80

T30

80

T14

10

values[0x0]

all_enables

biggest_size

158306

1

T1

5

T2

7

T5

7

values[0x1]

all_enables

biggest_size

157405

1

T1

3

T2

4

T5

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5706	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	19820	1		T3	4		T41	3		T42	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10921	1		T55	6		T57	3		T51	35
values[0x0]	7074	1		T3	9		T41	7		T42	1
values[0x1]	7531	1		T3	7		T41	3		T42	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4399	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	21127	1		T3	5		T41	3		T42	2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	139	1		T56	2		T88	10		T89	1
valid_sources[0x01]	102	1		T126	1		T51	1		T88	8
valid_sources[0x02]	117	1		T126	1		T63	2		T56	1
valid_sources[0x03]	151	1		T144	2		T88	6		T52	2
valid_sources[0x04]	217	1		T55	2		T56	2		T88	8
valid_sources[0x05]	96	1		T145	1		T88	4		T91	1
valid_sources[0x06]	76	1		T146	3		T88	4		T91	1
valid_sources[0x07]	67	1		T50	1		T88	4		T76	3
valid_sources[0x08]	70	1		T51	1		T56	1		T88	6
valid_sources[0x09]	89	1		T77	1		T87	1		T88	6
valid_sources[0x0a]	222	1		T88	4		T53	3		T83	2
valid_sources[0x0b]	82	1		T126	1		T88	12		T89	1
valid_sources[0x0c]	109	1		T60	3		T147	1		T148	1
valid_sources[0x0d]	63	1		T126	1		T88	4		T89	1
valid_sources[0x0e]	93	1		T54	18		T88	2		T76	10
valid_sources[0x0f]	82	1		T56	1		T88	2		T84	1
valid_sources[0x10]	76	1		T50	1		T77	1		T59	9
valid_sources[0x11]	110	1		T54	2		T88	8		T76	8
valid_sources[0x12]	60	1		T77	2		T82	1		T83	2
valid_sources[0x13]	67	1		T126	1		T88	4		T89	1
valid_sources[0x14]	164	1		T55	1		T54	27		T88	5
valid_sources[0x15]	106	1		T88	2		T76	4		T83	6
valid_sources[0x16]	105	1		T123	4		T88	8		T89	1
valid_sources[0x17]	268	1		T88	4		T52	129		T76	3
valid_sources[0x18]	77	1		T88	2		T76	1		T83	1
valid_sources[0x19]	160	1		T50	1		T88	4		T90	3
valid_sources[0x1a]	80	1		T88	2		T76	1		T90	1
valid_sources[0x1b]	87	1		T77	1		T147	1		T149	3
valid_sources[0x1c]	136	1		T47	2		T48	1		T124	1
valid_sources[0x1d]	62	1		T124	2		T51	1		T88	4
valid_sources[0x1e]	104	1		T147	1		T88	8		T150	1
valid_sources[0x1f]	74	1		T144	1		T51	1		T88	4
valid_sources[0x20]	74	1		T151	1		T88	4		T83	9
valid_sources[0x21]	106	1		T41	1		T148	1		T51	5
valid_sources[0x22]	82	1		T41	1		T88	6		T94	10
valid_sources[0x23]	117	1		T88	8		T76	4		T53	2
valid_sources[0x24]	189	1		T147	1		T51	1		T56	2
valid_sources[0x25]	60	1		T152	7		T147	2		T151	1
valid_sources[0x26]	97	1		T88	4		T52	2		T76	3
valid_sources[0x27]	270	1		T88	4		T52	210		T76	1
valid_sources[0x28]	82	1		T54	18		T88	4		T76	1
valid_sources[0x29]	86	1		T51	2		T88	8		T94	2
valid_sources[0x2a]	99	1		T47	1		T151	1		T88	4
valid_sources[0x2b]	76	1		T153	1		T154	5		T55	2
valid_sources[0x2c]	63	1		T48	1		T88	2		T76	3
valid_sources[0x2d]	108	1		T88	4		T52	2		T91	3
valid_sources[0x2e]	107	1		T55	1		T51	7		T54	23
valid_sources[0x2f]	90	1		T80	1		T155	3		T88	14
valid_sources[0x30]	57	1		T88	4		T76	2		T84	1
valid_sources[0x31]	89	1		T88	12		T89	1		T76	1
valid_sources[0x32]	68	1		T51	2		T88	3		T94	6
valid_sources[0x33]	87	1		T51	1		T88	2		T76	2
valid_sources[0x34]	193	1		T41	1		T53	1		T91	1
valid_sources[0x35]	89	1		T124	1		T51	8		T88	4
valid_sources[0x36]	129	1		T51	1		T88	2		T76	2
valid_sources[0x37]	72	1		T65	4		T88	8		T150	1
valid_sources[0x38]	90	1		T66	1		T88	3		T89	1
valid_sources[0x39]	45	1		T56	1		T84	2		T150	1
valid_sources[0x3a]	105	1		T156	1		T55	1		T51	3
valid_sources[0x3b]	103	1		T77	1		T152	2		T147	1
valid_sources[0x3c]	73	1		T146	1		T56	3		T88	4
valid_sources[0x3d]	78	1		T145	1		T88	6		T70	17
valid_sources[0x3e]	69	1		T51	2		T88	2		T76	2
valid_sources[0x3f]	70	1		T80	1		T88	4		T52	8
valid_sources[0x40]	83	1		T77	1		T124	3		T51	2
valid_sources[0x41]	75	1		T42	1		T151	1		T51	2
valid_sources[0x42]	104	1		T41	1		T144	1		T51	2
valid_sources[0x43]	79	1		T88	4		T76	1		T83	1
valid_sources[0x44]	60	1		T148	1		T88	2		T53	1
valid_sources[0x45]	84	1		T57	1		T56	1		T90	2
valid_sources[0x46]	119	1		T124	2		T51	3		T88	6
valid_sources[0x47]	76	1		T50	1		T88	2		T91	1
valid_sources[0x48]	98	1		T56	1		T88	4		T81	1
valid_sources[0x49]	107	1		T88	2		T76	13		T81	3
valid_sources[0x4a]	114	1		T77	1		T88	4		T89	2
valid_sources[0x4b]	130	1		T155	4		T88	6		T76	1
valid_sources[0x4c]	37	1		T51	1		T88	2		T150	1
valid_sources[0x4d]	131	1		T63	2		T157	3		T88	2
valid_sources[0x4e]	124	1		T47	1		T144	1		T88	6
valid_sources[0x4f]	93	1		T125	1		T51	1		T88	12
valid_sources[0x50]	119	1		T60	2		T54	9		T88	12
valid_sources[0x51]	91	1		T88	6		T76	6		T90	2
valid_sources[0x52]	70	1		T126	1		T56	2		T76	3
valid_sources[0x53]	85	1		T88	8		T89	1		T81	18
valid_sources[0x54]	66	1		T88	7		T76	3		T94	1
valid_sources[0x55]	93	1		T80	1		T158	13		T88	8
valid_sources[0x56]	70	1		T88	6		T150	2		T159	1
valid_sources[0x57]	69	1		T145	1		T160	2		T88	8
valid_sources[0x58]	98	1		T51	1		T88	10		T76	2
valid_sources[0x59]	82	1		T88	8		T83	4		T86	1
valid_sources[0x5a]	87	1		T161	1		T144	1		T88	2
valid_sources[0x5b]	57	1		T162	3		T51	1		T76	1
valid_sources[0x5c]	54	1		T154	2		T88	4		T76	9
valid_sources[0x5d]	92	1		T56	4		T88	2		T76	1
valid_sources[0x5e]	69	1		T55	1		T88	4		T52	2
valid_sources[0x5f]	81	1		T51	2		T88	8		T150	1
valid_sources[0x60]	66	1		T47	1		T88	4		T76	4
valid_sources[0x61]	71	1		T80	2		T88	2		T76	2
valid_sources[0x62]	128	1		T144	1		T85	85		T94	2
valid_sources[0x63]	72	1		T151	1		T144	1		T88	4
valid_sources[0x64]	82	1		T88	4		T53	2		T91	2
valid_sources[0x65]	101	1		T50	1		T55	1		T88	2
valid_sources[0x66]	138	1		T146	3		T54	41		T88	4
valid_sources[0x67]	95	1		T51	2		T88	6		T89	1
valid_sources[0x68]	77	1		T125	1		T66	2		T57	1
valid_sources[0x69]	57	1		T79	1		T91	1		T95	1
valid_sources[0x6a]	250	1		T88	11		T52	146		T76	1
valid_sources[0x6b]	129	1		T51	2		T88	4		T76	3
valid_sources[0x6c]	141	1		T126	1		T56	1		T88	2
valid_sources[0x6d]	67	1		T41	1		T150	1		T104	1
valid_sources[0x6e]	89	1		T151	1		T88	4		T91	1
valid_sources[0x6f]	75	1		T126	1		T88	10		T84	2
valid_sources[0x70]	74	1		T50	1		T88	4		T76	2
valid_sources[0x71]	106	1		T77	1		T147	1		T51	1
valid_sources[0x72]	39	1		T88	2		T76	2		T70	2
valid_sources[0x73]	146	1		T125	1		T88	2		T76	5
valid_sources[0x74]	66	1		T88	4		T76	4		T84	1
valid_sources[0x75]	101	1		T88	8		T53	1		T70	2
valid_sources[0x76]	118	1		T79	1		T60	6		T147	1
valid_sources[0x77]	79	1		T82	1		T94	8		T104	5
valid_sources[0x78]	87	1		T77	1		T51	3		T88	8
valid_sources[0x79]	79	1		T76	3		T150	2		T159	2
valid_sources[0x7a]	83	1		T145	1		T147	2		T51	1
valid_sources[0x7b]	82	1		T41	1		T124	2		T88	4
valid_sources[0x7c]	80	1		T51	1		T88	2		T89	1
valid_sources[0x7d]	205	1		T51	2		T88	2		T52	4
valid_sources[0x7e]	84	1		T88	8		T70	4		T82	1
valid_sources[0x7f]	95	1		T78	1		T88	6		T76	2
valid_sources[0x80]	83	1		T51	1		T88	4		T76	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7267

1

T55

5

T57

1

T51

33

values[0x0]

all_enables

biggest_size

6284

1

T3

4

T41

2

T42

1

values[0x1]

all_enables

biggest_size

6269

1

T41

1

T77

3

T126

1