SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 868624 | 1 | T1 | 39 | T2 | 29 | T5 | 31 | |||
auto[1] | 17650 | 1 | T29 | 80 | T30 | 80 | T51 | 29 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 886062 | 1 | T1 | 39 | T2 | 29 | T29 | 80 | |||
values[1] | 24 | 1 | T95 | 1 | T130 | 2 | T131 | 1 | |||
values[2] | 2 | 1 | T132 | 1 | T133 | 1 | - | - | |||
values[3] | 115 | 1 | T53 | 5 | T81 | 6 | T95 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 886059 | 1 | T1 | 39 | T2 | 29 | T29 | 80 | |||
values[1] | 19 | 1 | T130 | 2 | T131 | 1 | T134 | 1 | |||
values[2] | 9 | 1 | T81 | 1 | T135 | 1 | T131 | 1 | |||
values[3] | 111 | 1 | T53 | 6 | T81 | 5 | T95 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 885954 | 1 | T1 | 39 | T2 | 29 | T29 | 80 | |||
auto[TlIntgErrCmd] | 105 | 1 | T53 | 3 | T81 | 7 | T95 | 5 | |||
auto[TlIntgErrData] | 108 | 1 | T53 | 4 | T81 | 9 | T95 | 2 | |||
auto[TlIntgErrBoth] | 107 | 1 | T53 | 3 | T81 | 4 | T95 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 38672 | 0 | T3 | 16 | T41 | 10 | T42 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 38449 | 1 | T3 | 16 | T41 | 10 | T42 | 3 | |||
values[1] | 20 | 1 | T81 | 1 | T84 | 1 | T135 | 2 | |||
values[2] | 6 | 1 | T84 | 1 | T131 | 1 | T133 | 1 | |||
values[3] | 113 | 1 | T53 | 5 | T81 | 11 | T95 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 38476 | 1 | T3 | 16 | T41 | 10 | T42 | 3 | |||
values[1] | 20 | 1 | T84 | 2 | T135 | 2 | T131 | 1 | |||
values[2] | 5 | 1 | T53 | 1 | T136 | 1 | T133 | 1 | |||
values[3] | 86 | 1 | T53 | 4 | T81 | 4 | T95 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 38352 | 1 | T3 | 16 | T41 | 10 | T42 | 3 | |||
auto[TlIntgErrCmd] | 124 | 1 | T53 | 2 | T81 | 11 | T95 | 2 | |||
auto[TlIntgErrData] | 97 | 1 | T53 | 2 | T81 | 2 | T95 | 4 | |||
auto[TlIntgErrBoth] | 99 | 1 | T53 | 6 | T81 | 7 | T95 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |