Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	256448	1		T1	31		T2	18		T5	22
full_word	629826	1		T1	8		T2	11		T29	80

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	885954	1		T1	39		T2	29		T29	80
auto[TlIntgErrCmd]	105	1		T53	3		T81	7		T95	5
auto[TlIntgErrData]	108	1		T53	4		T81	9		T95	2
auto[TlIntgErrBoth]	107	1		T53	3		T81	4		T95	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	528653	1		T29	80		T30	80		T14	21
auto[1]	357621	1		T1	39		T2	29		T5	31

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	215701	1		T14	11		T36	5		T15	3
auto[TlIntgErrNone]	partial	auto[1]	40451	1		T1	31		T2	18		T5	22
auto[TlIntgErrNone]	full_word	auto[0]	312826	1		T29	80		T30	80		T14	10
auto[TlIntgErrNone]	full_word	auto[1]	316976	1		T1	8		T2	11		T5	9
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T81	2		T95	3		T135	2
auto[TlIntgErrCmd]	partial	auto[1]	62	1		T53	3		T81	4		T95	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T135	1		T133	1		T137	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T81	1		T138	1		T139	2
auto[TlIntgErrData]	partial	auto[0]	50	1		T53	1		T81	5		T95	2
auto[TlIntgErrData]	partial	auto[1]	54	1		T53	3		T81	3		T84	4
auto[TlIntgErrData]	full_word	auto[0]	3	1		T81	1		T133	1		T140	1
auto[TlIntgErrData]	full_word	auto[1]	1	1		T131	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T53	2		T81	2		T95	1
auto[TlIntgErrBoth]	partial	auto[1]	65	1		T53	1		T81	2		T95	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T84	1		T130	2		T132	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1		T84	1		T131	1		T132	1