Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.03	90.91	61.70	87.88		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	50346325	11731	0	0
late_debug_enable_rd_A	50346325	2031	0	0
late_debug_enable_regwen_rd_A	50346325	2018	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50346325	11731	0	0
T51	17131	93	0	0
T52	104731	1105	0	0
T53	40055	3	0	0
T54	11749	168	0	0
T70	419131	59	0	0
T76	23435	624	0	0
T81	81120	4	0	0
T82	291803	13	0	0
T83	5421	54	0	0
T84	118987	8	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50346325	2031	0	0
T53	40055	43	0	0
T54	11749	85	0	0
T56	39229	43	0	0
T57	6388	7	0	0
T76	23435	153	0	0
T81	81120	104	0	0
T84	118987	73	0	0
T86	8906	41	0	0
T90	53984	21	0	0
T93	8578	4	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50346325	2018	0	0
T53	40055	43	0	0
T54	11749	42	0	0
T56	39229	45	0	0
T57	6388	6	0	0
T76	23435	182	0	0
T81	81120	71	0	0
T84	118987	66	0	0
T86	8906	20	0	0
T90	53984	24	0	0
T93	8578	7	0	0