Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	96.30	100.00	88.89				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	96.30	100.00	88.89				100.00
tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T25,T45

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T25,T45
1	1	Covered	T1,T25,T45

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T25,T45
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	32172389	32171279	0	0
selKnown1	49603504	49602394	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	32172389	32171279	0	0
T1	57091	57087	0	0
T2	39719	39715	0	0
T3	344	340	0	0
T7	80182	80178	0	0
T9	241012	241008	0	0
T10	0	24	0	0
T12	0	28	0	0
T13	0	14	0	0
T21	0	10	0	0
T22	0	32	0	0
T23	0	50	0	0
T31	260	256	0	0
T38	0	40	0	0
T41	240	236	0	0
T42	222	218	0	0
T43	0	5	0	0
T47	218	214	0	0
T49	0	38	0	0
T50	218	214	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	49603504	49602394	0	0
T1	171099	171095	0	0
T2	168151	168147	0	0
T3	2027	2023	0	0
T7	74100	74096	0	0
T9	302884	302880	0	0
T10	0	24	0	0
T12	0	28	0	0
T13	0	14	0	0
T15	0	4	0	0
T22	0	32	0	0
T23	0	50	0	0
T31	2292	2288	0	0
T38	0	40	0	0
T41	1420	1416	0	0
T42	1627	1623	0	0
T47	1584	1580	0	0
T49	0	38	0	0
T50	1263	1259	0	0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T25,T45

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T25,T45
1	1	Covered	T1,T25,T45

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	13279463	13279292	0	0
selKnown1	30710760	30710589	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	13279463	13279292	0	0
T1	28339	28338	0	0
T2	19852	19851	0	0
T3	171	170	0	0
T7	40090	40089	0	0
T9	120505	120504	0	0
T31	129	128	0	0
T41	119	118	0	0
T42	110	109	0	0
T47	108	107	0	0
T50	108	107	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	30710760	30710589	0	0
T1	142346	142345	0	0
T2	148287	148286	0	0
T3	1854	1853	0	0
T7	34008	34007	0	0
T9	182377	182376	0	0
T31	2161	2160	0	0
T41	1299	1298	0	0
T42	1515	1514	0	0
T47	1474	1473	0	0
T50	1153	1152	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T25,T45

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T25,T45
1	1	Covered	T1,T25,T45

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	801	630	0	0
selKnown1	783	612	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	801	630	0	0
T1	2	1	0	0
T2	5	4	0	0
T3	1	0	0	0
T7	1	0	0	0
T9	1	0	0	0
T10	0	12	0	0
T12	0	14	0	0
T13	0	7	0	0
T22	0	16	0	0
T23	0	25	0	0
T31	1	0	0	0
T38	0	20	0	0
T41	1	0	0	0
T42	1	0	0	0
T43	0	5	0	0
T47	1	0	0	0
T49	0	19	0	0
T50	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	612	0	0
T1	3	2	0	0
T2	6	5	0	0
T3	1	0	0	0
T7	1	0	0	0
T9	1	0	0	0
T10	0	12	0	0
T12	0	14	0	0
T13	0	7	0	0
T15	0	2	0	0
T22	0	16	0	0
T23	0	25	0	0
T31	1	0	0	0
T38	0	20	0	0
T41	1	0	0	0
T42	1	0	0	0
T47	1	0	0	0
T49	0	19	0	0
T50	1	0	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T25,T45

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T25,T45
1	1	Covered	T1,T25,T45

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T25,T45
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	18889864	18889480	0	0
selKnown1	18889864	18889480	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	18889864	18889480	0	0
T1	28747	28746	0	0
T2	19852	19851	0	0
T3	171	170	0	0
T7	40090	40089	0	0
T9	120505	120504	0	0
T31	129	128	0	0
T41	119	118	0	0
T42	110	109	0	0
T47	108	107	0	0
T50	108	107	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	18889864	18889480	0	0
T1	28747	28746	0	0
T2	19852	19851	0	0
T3	171	170	0	0
T7	40090	40089	0	0
T9	120505	120504	0	0
T31	129	128	0	0
T41	119	118	0	0
T42	110	109	0	0
T47	108	107	0	0
T50	108	107	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T25,T45

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T25,T45
1	1	Covered	T1,T25,T45

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T25,T45
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	2261	1877	0	0
selKnown1	2097	1713	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	2261	1877	0	0
T1	3	2	0	0
T2	10	9	0	0
T3	1	0	0	0
T7	1	0	0	0
T9	1	0	0	0
T10	0	12	0	0
T12	0	14	0	0
T13	0	7	0	0
T21	0	10	0	0
T22	0	16	0	0
T23	0	25	0	0
T31	1	0	0	0
T38	0	20	0	0
T41	1	0	0	0
T42	1	0	0	0
T47	1	0	0	0
T49	0	19	0	0
T50	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2097	1713	0	0
T1	3	2	0	0
T2	6	5	0	0
T3	1	0	0	0
T7	1	0	0	0
T9	1	0	0	0
T10	0	12	0	0
T12	0	14	0	0
T13	0	7	0	0
T15	0	2	0	0
T22	0	16	0	0
T23	0	25	0	0
T31	1	0	0	0
T38	0	20	0	0
T41	1	0	0	0
T42	1	0	0	0
T47	1	0	0	0
T49	0	19	0	0
T50	1	0	0	0