Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	208403	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	583105	1		T4	1		T5	16		T20	11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	483774	1		T5	24		T20	8		T7	8
values[0x0]	151383	1		T4	2		T5	14		T20	5
values[0x1]	156351	1		T4	2		T5	18		T20	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	160564	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	630944	1		T4	1		T5	22		T20	11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2908	1		T33	1		T42	114		T43	196
valid_sources[0x01]	2993	1		T25	2		T34	1		T42	100
valid_sources[0x02]	3246	1		T5	1		T54	1		T38	1
valid_sources[0x03]	3212	1		T42	108		T43	251		T44	14
valid_sources[0x04]	3146	1		T8	1		T134	1		T54	2
valid_sources[0x05]	3660	1		T8	1		T42	124		T43	186
valid_sources[0x06]	3502	1		T54	1		T42	84		T43	232
valid_sources[0x07]	2777	1		T20	1		T6	1		T34	1
valid_sources[0x08]	3131	1		T5	1		T12	9		T42	100
valid_sources[0x09]	4155	1		T135	1		T42	115		T43	174
valid_sources[0x0a]	3182	1		T5	1		T42	129		T43	222
valid_sources[0x0b]	3118	1		T54	1		T42	129		T43	229
valid_sources[0x0c]	2910	1		T54	1		T38	1		T42	102
valid_sources[0x0d]	2843	1		T5	5		T8	1		T54	1
valid_sources[0x0e]	3174	1		T8	1		T33	3		T42	89
valid_sources[0x0f]	3263	1		T20	1		T54	1		T42	98
valid_sources[0x10]	2991	1		T54	1		T42	93		T43	199
valid_sources[0x11]	3227	1		T34	1		T42	91		T43	221
valid_sources[0x12]	3071	1		T33	3		T42	116		T43	194
valid_sources[0x13]	3375	1		T6	1		T111	38		T54	1
valid_sources[0x14]	3190	1		T54	1		T42	93		T43	152
valid_sources[0x15]	3359	1		T54	1		T38	1		T42	105
valid_sources[0x16]	2851	1		T20	2		T33	2		T42	96
valid_sources[0x17]	2971	1		T5	3		T33	1		T42	108
valid_sources[0x18]	2848	1		T42	119		T43	227		T44	35
valid_sources[0x19]	2915	1		T33	1		T42	84		T43	204
valid_sources[0x1a]	3526	1		T42	119		T43	260		T44	7
valid_sources[0x1b]	3195	1		T6	1		T42	112		T43	208
valid_sources[0x1c]	3193	1		T34	1		T42	92		T43	209
valid_sources[0x1d]	3003	1		T54	1		T38	1		T42	91
valid_sources[0x1e]	3002	1		T25	1		T134	1		T42	119
valid_sources[0x1f]	2806	1		T33	3		T42	112		T43	174
valid_sources[0x20]	3019	1		T8	1		T54	1		T34	1
valid_sources[0x21]	2863	1		T33	6		T54	1		T42	94
valid_sources[0x22]	3203	1		T8	1		T42	101		T43	185
valid_sources[0x23]	2867	1		T136	2		T42	87		T43	164
valid_sources[0x24]	2982	1		T42	89		T43	242		T44	30
valid_sources[0x25]	2990	1		T8	2		T42	82		T43	216
valid_sources[0x26]	2951	1		T33	1		T54	3		T42	103
valid_sources[0x27]	3020	1		T54	1		T42	118		T43	232
valid_sources[0x28]	3107	1		T5	2		T8	1		T42	103
valid_sources[0x29]	2834	1		T8	1		T42	103		T43	196
valid_sources[0x2a]	3242	1		T13	34		T34	1		T42	100
valid_sources[0x2b]	2725	1		T8	1		T54	2		T42	100
valid_sources[0x2c]	3238	1		T12	24		T134	1		T54	1
valid_sources[0x2d]	2834	1		T42	121		T43	169		T44	13
valid_sources[0x2e]	3371	1		T25	1		T33	9		T34	1
valid_sources[0x2f]	3519	1		T5	2		T33	1		T54	1
valid_sources[0x30]	3023	1		T25	1		T33	6		T137	8
valid_sources[0x31]	2815	1		T54	1		T42	87		T43	194
valid_sources[0x32]	3144	1		T42	93		T43	240		T44	10
valid_sources[0x33]	2887	1		T54	1		T42	90		T43	198
valid_sources[0x34]	3101	1		T25	1		T42	91		T43	217
valid_sources[0x35]	2765	1		T54	1		T34	1		T42	91
valid_sources[0x36]	3032	1		T5	1		T8	1		T54	2
valid_sources[0x37]	3240	1		T8	1		T54	1		T38	1
valid_sources[0x38]	3118	1		T5	4		T54	2		T42	91
valid_sources[0x39]	3058	1		T5	2		T6	1		T42	105
valid_sources[0x3a]	2983	1		T5	1		T6	3		T25	1
valid_sources[0x3b]	3198	1		T5	1		T6	1		T25	2
valid_sources[0x3c]	2817	1		T54	1		T42	115		T43	201
valid_sources[0x3d]	2841	1		T33	1		T54	1		T42	106
valid_sources[0x3e]	2920	1		T6	1		T25	1		T12	3
valid_sources[0x3f]	2878	1		T8	1		T42	91		T43	213
valid_sources[0x40]	3256	1		T33	1		T42	88		T43	226
valid_sources[0x41]	4276	1		T5	3		T8	1		T33	3
valid_sources[0x42]	2735	1		T33	1		T54	1		T34	2
valid_sources[0x43]	2769	1		T8	1		T42	110		T43	135
valid_sources[0x44]	2758	1		T8	1		T25	1		T42	114
valid_sources[0x45]	3314	1		T5	1		T42	116		T43	262
valid_sources[0x46]	2859	1		T5	1		T20	1		T9	2
valid_sources[0x47]	2935	1		T8	2		T54	1		T38	1
valid_sources[0x48]	3315	1		T6	1		T135	1		T42	132
valid_sources[0x49]	2938	1		T5	2		T8	1		T6	1
valid_sources[0x4a]	3051	1		T5	2		T6	1		T54	1
valid_sources[0x4b]	2948	1		T8	2		T34	1		T42	78
valid_sources[0x4c]	3003	1		T54	1		T42	113		T43	261
valid_sources[0x4d]	3121	1		T33	5		T34	1		T42	108
valid_sources[0x4e]	2909	1		T33	2		T54	1		T42	115
valid_sources[0x4f]	3585	1		T8	1		T42	106		T43	173
valid_sources[0x50]	3073	1		T5	1		T6	1		T25	4
valid_sources[0x51]	3246	1		T12	9		T34	1		T42	110
valid_sources[0x52]	3299	1		T25	1		T33	1		T54	1
valid_sources[0x53]	3275	1		T42	114		T43	236		T44	15
valid_sources[0x54]	3229	1		T6	1		T25	1		T54	1
valid_sources[0x55]	2960	1		T33	2		T34	1		T42	106
valid_sources[0x56]	3114	1		T33	4		T42	85		T43	170
valid_sources[0x57]	3081	1		T34	1		T42	113		T43	237
valid_sources[0x58]	3075	1		T134	1		T42	126		T43	196
valid_sources[0x59]	2773	1		T42	118		T43	219		T44	43
valid_sources[0x5a]	3284	1		T34	1		T38	1		T42	109
valid_sources[0x5b]	2997	1		T8	1		T42	85		T43	193
valid_sources[0x5c]	3442	1		T42	86		T43	297		T44	25
valid_sources[0x5d]	2897	1		T20	1		T8	1		T55	1
valid_sources[0x5e]	3300	1		T42	115		T43	205		T44	12
valid_sources[0x5f]	2834	1		T134	1		T42	95		T43	179
valid_sources[0x60]	3133	1		T6	1		T54	3		T42	126
valid_sources[0x61]	2917	1		T33	1		T134	1		T42	105
valid_sources[0x62]	2910	1		T134	1		T42	86		T43	216
valid_sources[0x63]	3229	1		T6	1		T33	2		T34	3
valid_sources[0x64]	2775	1		T9	1		T42	104		T43	167
valid_sources[0x65]	3255	1		T8	1		T33	10		T34	1
valid_sources[0x66]	2915	1		T25	1		T12	21		T42	86
valid_sources[0x67]	3154	1		T8	2		T12	1		T33	2
valid_sources[0x68]	2975	1		T6	1		T42	94		T43	191
valid_sources[0x69]	2926	1		T8	2		T134	1		T54	1
valid_sources[0x6a]	3145	1		T42	92		T43	278		T44	23
valid_sources[0x6b]	2889	1		T8	1		T33	2		T54	1
valid_sources[0x6c]	3435	1		T25	1		T38	1		T42	112
valid_sources[0x6d]	3337	1		T42	82		T43	190		T44	31
valid_sources[0x6e]	2961	1		T5	2		T8	1		T54	1
valid_sources[0x6f]	2958	1		T5	1		T8	1		T38	1
valid_sources[0x70]	3209	1		T9	1		T42	133		T43	199
valid_sources[0x71]	3077	1		T34	1		T42	92		T43	244
valid_sources[0x72]	2873	1		T42	120		T43	188		T44	5
valid_sources[0x73]	2848	1		T5	1		T6	1		T25	5
valid_sources[0x74]	2823	1		T134	1		T34	2		T42	110
valid_sources[0x75]	2886	1		T42	91		T43	254		T44	24
valid_sources[0x76]	3154	1		T8	1		T38	1		T42	90
valid_sources[0x77]	2953	1		T42	103		T43	225		T44	43
valid_sources[0x78]	2979	1		T8	1		T33	1		T34	1
valid_sources[0x79]	2737	1		T54	1		T42	91		T43	163
valid_sources[0x7a]	3637	1		T5	1		T6	1		T134	1
valid_sources[0x7b]	2854	1		T33	1		T42	119		T43	243
valid_sources[0x7c]	2911	1		T20	1		T12	10		T33	1
valid_sources[0x7d]	2908	1		T34	1		T42	82		T43	243
valid_sources[0x7e]	2938	1		T8	1		T33	3		T42	84
valid_sources[0x7f]	2936	1		T42	111		T43	184		T44	24
valid_sources[0x80]	2913	1		T54	1		T42	92		T43	154

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

284702

1

T5

11

T20

3

T7

2

values[0x0]

all_enables

biggest_size

149397

1

T4

1

T5

4

T20

5

values[0x1]

all_enables

biggest_size

149006

1

T5

1

T20

3

T8

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5160	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	19707	1		T2	2		T27	4		T32	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10062	1		T38	13		T42	568		T43	568
values[0x0]	7330	1		T2	2		T27	11		T36	2
values[0x1]	7475	1		T2	8		T27	1		T32	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4010	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	20857	1		T2	4		T27	4		T32	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	66	1		T61	1		T42	3		T43	2
valid_sources[0x01]	72	1		T42	3		T43	1		T39	1
valid_sources[0x02]	53	1		T42	6		T43	3		T75	1
valid_sources[0x03]	138	1		T138	2		T42	1		T43	3
valid_sources[0x04]	80	1		T139	1		T138	2		T42	2
valid_sources[0x05]	86	1		T45	2		T42	3		T43	1
valid_sources[0x06]	88	1		T140	2		T42	4		T43	2
valid_sources[0x07]	65	1		T42	5		T43	4		T39	3
valid_sources[0x08]	54	1		T42	3		T43	1		T63	1
valid_sources[0x09]	103	1		T27	2		T42	3		T43	1
valid_sources[0x0a]	130	1		T141	2		T142	1		T38	11
valid_sources[0x0b]	69	1		T61	1		T42	1		T43	1
valid_sources[0x0c]	63	1		T139	1		T42	4		T43	2
valid_sources[0x0d]	69	1		T42	3		T43	4		T80	5
valid_sources[0x0e]	99	1		T42	2		T43	4		T39	1
valid_sources[0x0f]	162	1		T38	48		T42	4		T43	5
valid_sources[0x10]	65	1		T143	2		T42	2		T43	1
valid_sources[0x11]	62	1		T42	4		T43	2		T40	1
valid_sources[0x12]	84	1		T62	6		T42	1		T43	5
valid_sources[0x13]	71	1		T42	4		T43	1		T39	2
valid_sources[0x14]	79	1		T144	2		T142	4		T42	2
valid_sources[0x15]	71	1		T141	1		T42	7		T43	2
valid_sources[0x16]	103	1		T43	1		T39	1		T40	9
valid_sources[0x17]	70	1		T2	2		T145	8		T43	3
valid_sources[0x18]	106	1		T72	2		T43	3		T40	3
valid_sources[0x19]	56	1		T43	1		T79	2		T40	1
valid_sources[0x1a]	79	1		T146	1		T147	2		T42	5
valid_sources[0x1b]	96	1		T42	2		T43	2		T63	1
valid_sources[0x1c]	83	1		T148	1		T42	5		T43	2
valid_sources[0x1d]	67	1		T149	12		T42	3		T63	1
valid_sources[0x1e]	65	1		T148	1		T42	4		T43	4
valid_sources[0x1f]	51	1		T27	1		T150	1		T42	1
valid_sources[0x20]	92	1		T147	3		T142	1		T42	1
valid_sources[0x21]	81	1		T2	1		T43	3		T39	1
valid_sources[0x22]	53	1		T42	3		T43	1		T39	1
valid_sources[0x23]	874	1		T42	4		T43	4		T41	27
valid_sources[0x24]	69	1		T42	6		T43	3		T39	1
valid_sources[0x25]	71	1		T27	2		T139	1		T42	1
valid_sources[0x26]	68	1		T146	2		T148	1		T42	3
valid_sources[0x27]	60	1		T141	1		T42	3		T39	2
valid_sources[0x28]	207	1		T151	1		T152	1		T43	5
valid_sources[0x29]	74	1		T153	1		T42	1		T43	2
valid_sources[0x2a]	202	1		T154	2		T43	2		T74	10
valid_sources[0x2b]	71	1		T42	1		T43	1		T40	3
valid_sources[0x2c]	86	1		T155	1		T156	1		T42	4
valid_sources[0x2d]	59	1		T42	1		T39	1		T41	1
valid_sources[0x2e]	79	1		T42	4		T43	5		T75	9
valid_sources[0x2f]	57	1		T42	1		T43	4		T73	2
valid_sources[0x30]	71	1		T66	1		T43	3		T40	5
valid_sources[0x31]	94	1		T45	1		T70	1		T148	1
valid_sources[0x32]	72	1		T2	1		T42	1		T43	1
valid_sources[0x33]	74	1		T40	5		T73	1		T74	7
valid_sources[0x34]	822	1		T27	1		T39	2		T40	3
valid_sources[0x35]	94	1		T143	2		T42	2		T43	3
valid_sources[0x36]	179	1		T45	1		T148	1		T42	3
valid_sources[0x37]	68	1		T42	1		T43	3		T41	1
valid_sources[0x38]	71	1		T150	1		T42	2		T43	2
valid_sources[0x39]	54	1		T154	2		T42	2		T43	2
valid_sources[0x3a]	122	1		T150	1		T138	2		T42	3
valid_sources[0x3b]	64	1		T39	3		T40	1		T75	3
valid_sources[0x3c]	81	1		T42	3		T43	2		T40	1
valid_sources[0x3d]	150	1		T142	3		T43	1		T44	5
valid_sources[0x3e]	58	1		T42	2		T63	2		T75	5
valid_sources[0x3f]	89	1		T43	2		T39	3		T73	2
valid_sources[0x40]	126	1		T152	3		T42	2		T43	3
valid_sources[0x41]	76	1		T42	4		T39	4		T63	1
valid_sources[0x42]	100	1		T42	3		T43	3		T39	1
valid_sources[0x43]	64	1		T42	2		T43	3		T39	3
valid_sources[0x44]	68	1		T38	1		T42	1		T39	2
valid_sources[0x45]	83	1		T157	4		T158	3		T42	5
valid_sources[0x46]	92	1		T42	4		T43	1		T39	1
valid_sources[0x47]	69	1		T159	2		T42	3		T43	4
valid_sources[0x48]	61	1		T42	2		T43	2		T63	1
valid_sources[0x49]	103	1		T153	1		T42	1		T43	2
valid_sources[0x4a]	116	1		T61	2		T160	3		T161	3
valid_sources[0x4b]	110	1		T157	3		T161	2		T42	3
valid_sources[0x4c]	106	1		T61	1		T42	1		T43	3
valid_sources[0x4d]	127	1		T2	1		T42	3		T43	2
valid_sources[0x4e]	102	1		T139	1		T154	1		T42	1
valid_sources[0x4f]	83	1		T42	1		T43	1		T44	4
valid_sources[0x50]	98	1		T140	2		T42	2		T43	4
valid_sources[0x51]	147	1		T42	1		T39	1		T40	2
valid_sources[0x52]	84	1		T146	1		T42	3		T43	1
valid_sources[0x53]	98	1		T162	1		T42	1		T43	1
valid_sources[0x54]	87	1		T42	3		T43	4		T39	1
valid_sources[0x55]	88	1		T42	2		T43	4		T44	2
valid_sources[0x56]	76	1		T139	1		T42	2		T43	3
valid_sources[0x57]	79	1		T139	1		T42	5		T43	1
valid_sources[0x58]	81	1		T148	1		T150	1		T42	4
valid_sources[0x59]	72	1		T42	4		T43	3		T40	5
valid_sources[0x5a]	69	1		T70	1		T43	1		T75	4
valid_sources[0x5b]	51	1		T139	1		T42	2		T43	1
valid_sources[0x5c]	66	1		T142	1		T42	6		T43	3
valid_sources[0x5d]	88	1		T61	1		T67	1		T63	1
valid_sources[0x5e]	320	1		T42	1		T43	4		T44	6
valid_sources[0x5f]	120	1		T152	1		T42	1		T43	3
valid_sources[0x60]	120	1		T42	1		T43	4		T39	2
valid_sources[0x61]	90	1		T2	1		T61	1		T42	2
valid_sources[0x62]	132	1		T153	1		T42	1		T43	1
valid_sources[0x63]	114	1		T139	1		T138	1		T42	1
valid_sources[0x64]	93	1		T42	2		T43	3		T40	2
valid_sources[0x65]	87	1		T42	2		T43	6		T63	1
valid_sources[0x66]	80	1		T42	7		T43	2		T39	1
valid_sources[0x67]	89	1		T139	1		T141	2		T42	1
valid_sources[0x68]	65	1		T146	1		T42	1		T43	2
valid_sources[0x69]	46	1		T27	1		T42	1		T40	2
valid_sources[0x6a]	68	1		T42	2		T43	3		T82	1
valid_sources[0x6b]	108	1		T42	2		T43	2		T39	1
valid_sources[0x6c]	89	1		T147	3		T42	4		T43	4
valid_sources[0x6d]	141	1		T36	2		T42	2		T43	2
valid_sources[0x6e]	73	1		T163	1		T147	1		T42	3
valid_sources[0x6f]	54	1		T42	1		T43	5		T39	1
valid_sources[0x70]	44	1		T40	1		T74	1		T75	3
valid_sources[0x71]	65	1		T42	1		T39	2		T40	2
valid_sources[0x72]	86	1		T164	10		T42	2		T43	3
valid_sources[0x73]	85	1		T42	2		T43	6		T39	1
valid_sources[0x74]	102	1		T151	2		T42	3		T43	2
valid_sources[0x75]	104	1		T42	2		T43	2		T63	2
valid_sources[0x76]	82	1		T42	4		T40	2		T65	3
valid_sources[0x77]	117	1		T70	1		T42	3		T43	1
valid_sources[0x78]	117	1		T139	1		T158	1		T42	4
valid_sources[0x79]	56	1		T138	1		T42	1		T43	5
valid_sources[0x7a]	76	1		T71	6		T42	1		T43	1
valid_sources[0x7b]	82	1		T42	5		T43	6		T39	1
valid_sources[0x7c]	131	1		T42	1		T43	1		T74	38
valid_sources[0x7d]	82	1		T155	1		T42	2		T43	4
valid_sources[0x7e]	74	1		T67	3		T42	2		T40	3
valid_sources[0x7f]	91	1		T42	3		T43	2		T63	1
valid_sources[0x80]	67	1		T42	2		T43	2		T63	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6906

1

T38

13

T42

275

T43

271

values[0x0]

all_enables

biggest_size

6570

1

T2

1

T27

4

T36

1

values[0x1]

all_enables

biggest_size

6231

1

T2

1

T32

1

T45

1