Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	246912	1		T4	3		T5	40		T20	5
full_word	584516	1		T4	1		T5	16		T20	11

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	831138	1		T4	4		T5	56		T20	16
auto[TlIntgErrCmd]	102	1		T115	9		T116	4		T117	5
auto[TlIntgErrData]	90	1		T115	8		T116	2		T117	3
auto[TlIntgErrBoth]	98	1		T115	3		T116	4		T117	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	485370	1		T5	24		T20	8		T7	8
auto[1]	346058	1		T4	4		T5	32		T20	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	200401	1		T5	13		T20	5		T7	6
auto[TlIntgErrNone]	partial	auto[1]	46247	1		T4	3		T5	27		T7	1
auto[TlIntgErrNone]	full_word	auto[0]	284849	1		T5	11		T20	3		T7	2
auto[TlIntgErrNone]	full_word	auto[1]	299641	1		T4	1		T5	5		T20	8
auto[TlIntgErrCmd]	partial	auto[0]	39	1		T115	5		T116	1		T117	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1		T115	4		T116	2		T117	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T116	1		T130	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T131	1		T132	1		T129	1
auto[TlIntgErrData]	partial	auto[0]	40	1		T115	4		T117	1		T122	3
auto[TlIntgErrData]	partial	auto[1]	36	1		T115	3		T116	2		T117	2
auto[TlIntgErrData]	full_word	auto[0]	6	1		T122	2		T131	1		T126	1
auto[TlIntgErrData]	full_word	auto[1]	8	1		T115	1		T133	1		T123	3
auto[TlIntgErrBoth]	partial	auto[0]	31	1		T115	1		T116	1		T117	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1		T115	2		T116	3		T117	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T132	1		T130	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T122	1		T128	1		T123	1