Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	219882	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	593234	1		T2	6		T4	2		T5	24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	521706	1		T2	4		T5	12		T7	8
values[0x0]	143869	1		T2	2		T4	2		T5	18
values[0x1]	147541	1		T2	2		T4	1		T5	30

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	166846	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	646270	1		T2	7		T4	2		T5	32

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3560	1		T18	2		T68	1		T44	6
valid_sources[0x01]	2967	1		T11	1		T47	1		T46	127
valid_sources[0x02]	3349	1		T11	3		T146	1		T64	56
valid_sources[0x03]	3484	1		T44	25		T47	13		T46	106
valid_sources[0x04]	3626	1		T9	1		T41	278		T46	128
valid_sources[0x05]	2750	1		T11	2		T41	33		T46	157
valid_sources[0x06]	3550	1		T14	5		T44	16		T41	21
valid_sources[0x07]	3664	1		T14	3		T44	7		T46	145
valid_sources[0x08]	3001	1		T46	156		T42	8		T89	7
valid_sources[0x09]	3372	1		T14	1		T44	5		T47	4
valid_sources[0x0a]	2782	1		T15	15		T47	7		T46	149
valid_sources[0x0b]	2903	1		T41	1		T45	7		T46	132
valid_sources[0x0c]	2905	1		T7	1		T9	1		T146	1
valid_sources[0x0d]	2805	1		T11	1		T47	8		T46	146
valid_sources[0x0e]	3408	1		T9	1		T147	2		T41	32
valid_sources[0x0f]	3157	1		T47	5		T46	127		T42	25
valid_sources[0x10]	2803	1		T5	1		T44	1		T47	9
valid_sources[0x11]	2795	1		T46	132		T89	5		T90	34
valid_sources[0x12]	3517	1		T14	1		T44	3		T46	144
valid_sources[0x13]	4186	1		T36	36		T41	4		T46	149
valid_sources[0x14]	2947	1		T148	1		T44	5		T46	153
valid_sources[0x15]	3484	1		T9	1		T46	135		T42	12
valid_sources[0x16]	3387	1		T41	24		T46	130		T42	29
valid_sources[0x17]	2844	1		T41	11		T46	148		T42	10
valid_sources[0x18]	3223	1		T148	1		T47	3		T46	134
valid_sources[0x19]	2748	1		T14	6		T44	22		T46	164
valid_sources[0x1a]	2830	1		T44	4		T46	149		T90	35
valid_sources[0x1b]	3296	1		T44	3		T47	2		T46	113
valid_sources[0x1c]	3367	1		T44	10		T46	141		T42	39
valid_sources[0x1d]	3098	1		T46	147		T89	4		T90	6
valid_sources[0x1e]	2817	1		T15	8		T41	2		T46	130
valid_sources[0x1f]	3174	1		T15	3		T46	139		T42	5
valid_sources[0x20]	2889	1		T44	8		T41	12		T46	127
valid_sources[0x21]	2858	1		T23	34		T147	1		T44	4
valid_sources[0x22]	2832	1		T11	2		T146	1		T44	9
valid_sources[0x23]	2986	1		T41	16		T46	128		T42	25
valid_sources[0x24]	3045	1		T17	2		T146	1		T46	127
valid_sources[0x25]	3663	1		T44	11		T47	2		T46	116
valid_sources[0x26]	2705	1		T18	5		T14	1		T41	82
valid_sources[0x27]	2717	1		T44	20		T46	128		T42	2
valid_sources[0x28]	3242	1		T41	2		T46	146		T42	6
valid_sources[0x29]	3081	1		T11	1		T41	24		T46	118
valid_sources[0x2a]	3327	1		T13	1		T14	3		T146	3
valid_sources[0x2b]	2952	1		T68	1		T47	1		T41	95
valid_sources[0x2c]	2888	1		T44	1		T41	6		T46	122
valid_sources[0x2d]	3165	1		T41	128		T46	172		T42	14
valid_sources[0x2e]	3037	1		T44	21		T46	132		T42	3
valid_sources[0x2f]	3430	1		T47	12		T46	167		T42	276
valid_sources[0x30]	2984	1		T11	1		T44	8		T41	1
valid_sources[0x31]	3130	1		T11	1		T46	139		T42	3
valid_sources[0x32]	2642	1		T9	1		T44	15		T47	1
valid_sources[0x33]	3148	1		T11	4		T44	3		T41	2
valid_sources[0x34]	3262	1		T9	1		T44	2		T46	140
valid_sources[0x35]	2847	1		T41	3		T46	128		T89	9
valid_sources[0x36]	3140	1		T7	1		T41	21		T46	130
valid_sources[0x37]	4007	1		T68	1		T44	28		T41	274
valid_sources[0x38]	3025	1		T47	1		T41	19		T46	124
valid_sources[0x39]	2580	1		T41	9		T46	135		T42	7
valid_sources[0x3a]	3381	1		T44	9		T41	17		T46	140
valid_sources[0x3b]	2882	1		T46	135		T89	6		T90	18
valid_sources[0x3c]	3175	1		T7	1		T47	2		T41	51
valid_sources[0x3d]	2838	1		T83	1		T47	16		T41	21
valid_sources[0x3e]	3260	1		T5	34		T13	1		T15	7
valid_sources[0x3f]	4006	1		T46	168		T42	1		T89	2
valid_sources[0x40]	3306	1		T46	145		T42	26		T89	4
valid_sources[0x41]	2881	1		T24	5		T46	153		T42	33
valid_sources[0x42]	2779	1		T9	1		T14	4		T44	7
valid_sources[0x43]	2865	1		T47	4		T46	135		T42	7
valid_sources[0x44]	2851	1		T63	7		T14	3		T47	12
valid_sources[0x45]	2734	1		T24	4		T148	1		T44	12
valid_sources[0x46]	2554	1		T46	136		T42	5		T89	8
valid_sources[0x47]	2907	1		T46	131		T89	3		T90	18
valid_sources[0x48]	2886	1		T149	2		T46	148		T42	43
valid_sources[0x49]	2757	1		T146	1		T67	2		T44	2
valid_sources[0x4a]	2639	1		T46	116		T42	63		T89	3
valid_sources[0x4b]	3885	1		T11	2		T46	139		T89	4
valid_sources[0x4c]	2995	1		T11	1		T146	1		T41	64
valid_sources[0x4d]	3525	1		T14	2		T44	7		T41	275
valid_sources[0x4e]	3093	1		T41	18		T46	113		T42	281
valid_sources[0x4f]	3108	1		T44	11		T46	148		T89	1
valid_sources[0x50]	2678	1		T44	8		T41	13		T46	157
valid_sources[0x51]	3362	1		T24	3		T46	143		T42	325
valid_sources[0x52]	3350	1		T146	1		T46	157		T42	3
valid_sources[0x53]	2679	1		T47	7		T46	140		T89	3
valid_sources[0x54]	3570	1		T9	1		T146	1		T47	4
valid_sources[0x55]	3239	1		T41	2		T46	164		T42	63
valid_sources[0x56]	3118	1		T15	2		T14	2		T46	136
valid_sources[0x57]	3421	1		T2	8		T67	1		T44	3
valid_sources[0x58]	3180	1		T148	1		T44	4		T46	137
valid_sources[0x59]	3200	1		T41	4		T46	144		T42	18
valid_sources[0x5a]	2805	1		T24	23		T44	3		T47	4
valid_sources[0x5b]	2751	1		T65	1		T46	132		T42	5
valid_sources[0x5c]	3013	1		T7	3		T9	1		T146	4
valid_sources[0x5d]	3306	1		T41	291		T45	18		T46	144
valid_sources[0x5e]	2893	1		T44	6		T46	114		T42	35
valid_sources[0x5f]	2864	1		T44	2		T46	142		T42	15
valid_sources[0x60]	2838	1		T18	5		T44	31		T46	110
valid_sources[0x61]	3416	1		T15	8		T46	137		T42	277
valid_sources[0x62]	2612	1		T46	114		T42	8		T89	5
valid_sources[0x63]	2850	1		T68	1		T46	139		T89	1
valid_sources[0x64]	3531	1		T146	1		T41	15		T46	129
valid_sources[0x65]	2664	1		T148	1		T47	5		T46	138
valid_sources[0x66]	3830	1		T14	1		T11	1		T47	2
valid_sources[0x67]	2964	1		T44	15		T47	10		T46	125
valid_sources[0x68]	3766	1		T11	1		T147	1		T47	5
valid_sources[0x69]	2752	1		T148	1		T46	143		T89	4
valid_sources[0x6a]	3267	1		T46	138		T89	6		T90	25
valid_sources[0x6b]	3025	1		T46	125		T42	2		T89	7
valid_sources[0x6c]	3016	1		T46	158		T89	3		T90	35
valid_sources[0x6d]	3086	1		T41	274		T46	135		T42	94
valid_sources[0x6e]	3883	1		T148	2		T47	3		T46	141
valid_sources[0x6f]	2836	1		T14	2		T44	10		T47	4
valid_sources[0x70]	2925	1		T9	1		T46	152		T89	4
valid_sources[0x71]	5232	1		T41	2		T46	92		T42	19
valid_sources[0x72]	2783	1		T146	2		T47	25		T46	144
valid_sources[0x73]	2785	1		T44	5		T41	1		T46	135
valid_sources[0x74]	3008	1		T46	140		T42	9		T89	4
valid_sources[0x75]	2904	1		T14	3		T46	112		T42	77
valid_sources[0x76]	2813	1		T47	5		T41	11		T46	128
valid_sources[0x77]	2856	1		T9	1		T47	30		T41	14
valid_sources[0x78]	3678	1		T146	2		T44	1		T41	11
valid_sources[0x79]	3534	1		T44	3		T41	45		T46	142
valid_sources[0x7a]	3049	1		T47	1		T41	7		T46	152
valid_sources[0x7b]	3236	1		T9	1		T44	17		T46	133
valid_sources[0x7c]	3464	1		T11	2		T44	10		T41	49
valid_sources[0x7d]	3340	1		T46	124		T42	16		T89	5
valid_sources[0x7e]	3411	1		T15	13		T47	1		T41	48
valid_sources[0x7f]	2971	1		T5	5		T41	6		T46	158
valid_sources[0x80]	2996	1		T9	1		T41	23		T46	117

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

309967

1

T2

2

T5

2

T7

5

values[0x0]

all_enables

biggest_size

142079

1

T2

2

T4

2

T5

12

values[0x1]

all_enables

biggest_size

141188

1

T2

2

T5

10

T8

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5071	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	19629	1		T29	3		T30	2		T33	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9923	1		T44	75		T47	3		T41	32
values[0x0]	7345	1		T29	6		T30	6		T33	3
values[0x1]	7432	1		T29	3		T30	7		T31	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3851	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	20849	1		T29	3		T30	2		T33	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	64	1		T44	1		T46	2		T92	7
valid_sources[0x01]	80	1		T125	1		T150	1		T44	1
valid_sources[0x02]	63	1		T44	2		T46	1		T90	1
valid_sources[0x03]	69	1		T151	6		T152	1		T44	1
valid_sources[0x04]	60	1		T153	1		T44	4		T43	1
valid_sources[0x05]	118	1		T154	1		T44	1		T46	2
valid_sources[0x06]	52	1		T80	1		T46	1		T42	5
valid_sources[0x07]	65	1		T155	1		T46	3		T92	2
valid_sources[0x08]	83	1		T156	1		T44	2		T46	3
valid_sources[0x09]	159	1		T31	1		T44	2		T46	2
valid_sources[0x0a]	153	1		T44	1		T41	1		T46	1
valid_sources[0x0b]	89	1		T157	1		T44	7		T92	2
valid_sources[0x0c]	130	1		T57	15		T44	3		T46	1
valid_sources[0x0d]	67	1		T44	2		T46	1		T92	2
valid_sources[0x0e]	73	1		T30	1		T44	3		T46	1
valid_sources[0x0f]	47	1		T152	1		T41	1		T46	3
valid_sources[0x10]	107	1		T44	1		T41	1		T46	5
valid_sources[0x11]	537	1		T44	1		T46	7		T90	1
valid_sources[0x12]	194	1		T29	2		T80	2		T150	1
valid_sources[0x13]	73	1		T92	1		T84	9		T158	3
valid_sources[0x14]	47	1		T44	1		T92	2		T43	1
valid_sources[0x15]	90	1		T159	1		T42	6		T89	2
valid_sources[0x16]	85	1		T44	1		T92	3		T43	2
valid_sources[0x17]	103	1		T44	1		T90	1		T92	2
valid_sources[0x18]	114	1		T31	1		T41	1		T46	3
valid_sources[0x19]	76	1		T43	1		T94	2		T71	1
valid_sources[0x1a]	55	1		T44	2		T90	1		T92	4
valid_sources[0x1b]	378	1		T153	1		T44	2		T46	2
valid_sources[0x1c]	53	1		T44	2		T46	2		T92	3
valid_sources[0x1d]	42	1		T44	1		T46	6		T92	2
valid_sources[0x1e]	68	1		T160	13		T155	1		T42	1
valid_sources[0x1f]	114	1		T44	4		T41	2		T42	1
valid_sources[0x20]	169	1		T46	2		T92	4		T94	1
valid_sources[0x21]	71	1		T38	1		T44	1		T92	1
valid_sources[0x22]	127	1		T161	1		T162	1		T44	2
valid_sources[0x23]	43	1		T44	1		T92	2		T94	3
valid_sources[0x24]	71	1		T92	3		T93	1		T43	1
valid_sources[0x25]	72	1		T153	1		T44	1		T41	1
valid_sources[0x26]	77	1		T163	1		T44	1		T41	1
valid_sources[0x27]	84	1		T31	1		T44	1		T46	1
valid_sources[0x28]	68	1		T94	3		T95	1		T71	3
valid_sources[0x29]	79	1		T44	1		T92	4		T43	2
valid_sources[0x2a]	68	1		T161	2		T44	1		T46	3
valid_sources[0x2b]	58	1		T44	2		T46	1		T90	2
valid_sources[0x2c]	63	1		T125	1		T156	1		T44	1
valid_sources[0x2d]	105	1		T92	4		T94	2		T137	1
valid_sources[0x2e]	92	1		T81	1		T152	1		T157	13
valid_sources[0x2f]	72	1		T164	1		T44	4		T46	6
valid_sources[0x30]	67	1		T44	1		T46	2		T92	2
valid_sources[0x31]	99	1		T44	2		T41	1		T46	6
valid_sources[0x32]	53	1		T92	6		T43	1		T94	2
valid_sources[0x33]	60	1		T165	1		T44	1		T92	2
valid_sources[0x34]	63	1		T153	1		T44	1		T46	2
valid_sources[0x35]	66	1		T156	1		T46	1		T90	1
valid_sources[0x36]	67	1		T166	4		T44	1		T46	2
valid_sources[0x37]	82	1		T44	2		T41	1		T46	2
valid_sources[0x38]	70	1		T44	1		T90	1		T92	4
valid_sources[0x39]	78	1		T31	1		T44	1		T46	3
valid_sources[0x3a]	60	1		T167	8		T44	1		T92	3
valid_sources[0x3b]	47	1		T165	1		T156	1		T44	3
valid_sources[0x3c]	124	1		T44	1		T41	1		T92	3
valid_sources[0x3d]	54	1		T81	1		T41	1		T46	2
valid_sources[0x3e]	75	1		T46	1		T92	5		T94	4
valid_sources[0x3f]	84	1		T41	1		T92	3		T93	1
valid_sources[0x40]	59	1		T154	1		T44	4		T92	3
valid_sources[0x41]	99	1		T30	3		T44	1		T42	6
valid_sources[0x42]	136	1		T31	1		T44	3		T46	4
valid_sources[0x43]	70	1		T156	1		T92	4		T43	1
valid_sources[0x44]	66	1		T77	1		T44	2		T46	2
valid_sources[0x45]	63	1		T30	1		T31	1		T150	1
valid_sources[0x46]	47	1		T44	1		T46	2		T94	2
valid_sources[0x47]	79	1		T44	1		T46	2		T94	3
valid_sources[0x48]	49	1		T44	2		T46	6		T93	1
valid_sources[0x49]	70	1		T152	1		T44	1		T46	5
valid_sources[0x4a]	170	1		T163	1		T162	1		T168	1
valid_sources[0x4b]	99	1		T31	3		T168	1		T44	3
valid_sources[0x4c]	129	1		T46	1		T90	1		T43	1
valid_sources[0x4d]	90	1		T163	2		T162	1		T46	3
valid_sources[0x4e]	116	1		T77	2		T44	2		T46	3
valid_sources[0x4f]	114	1		T44	1		T90	1		T43	1
valid_sources[0x50]	48	1		T92	2		T43	1		T87	3
valid_sources[0x51]	99	1		T31	1		T92	10		T43	1
valid_sources[0x52]	193	1		T169	16		T44	1		T41	1
valid_sources[0x53]	56	1		T165	2		T170	1		T46	2
valid_sources[0x54]	181	1		T171	11		T172	15		T46	4
valid_sources[0x55]	59	1		T151	3		T155	1		T173	3
valid_sources[0x56]	95	1		T44	3		T46	1		T92	3
valid_sources[0x57]	110	1		T92	6		T43	1		T94	2
valid_sources[0x58]	49	1		T46	1		T90	1		T92	4
valid_sources[0x59]	195	1		T44	1		T41	2		T46	1
valid_sources[0x5a]	92	1		T92	4		T94	3		T71	1
valid_sources[0x5b]	59	1		T174	1		T45	2		T90	1
valid_sources[0x5c]	59	1		T163	1		T46	2		T43	2
valid_sources[0x5d]	304	1		T38	1		T44	1		T41	1
valid_sources[0x5e]	68	1		T30	1		T33	1		T175	1
valid_sources[0x5f]	73	1		T81	2		T44	1		T46	1
valid_sources[0x60]	70	1		T125	1		T153	1		T41	1
valid_sources[0x61]	991	1		T30	2		T92	1		T43	1
valid_sources[0x62]	135	1		T176	2		T44	1		T92	8
valid_sources[0x63]	48	1		T29	2		T78	3		T163	1
valid_sources[0x64]	93	1		T79	3		T165	1		T44	3
valid_sources[0x65]	79	1		T31	1		T161	1		T155	2
valid_sources[0x66]	51	1		T42	4		T90	1		T92	5
valid_sources[0x67]	90	1		T173	3		T44	1		T46	2
valid_sources[0x68]	85	1		T161	3		T163	1		T44	2
valid_sources[0x69]	90	1		T46	2		T92	7		T94	2
valid_sources[0x6a]	62	1		T165	1		T166	1		T46	4
valid_sources[0x6b]	69	1		T31	2		T154	1		T41	2
valid_sources[0x6c]	68	1		T44	2		T46	4		T95	5
valid_sources[0x6d]	68	1		T44	2		T41	1		T94	1
valid_sources[0x6e]	71	1		T44	3		T92	4		T43	1
valid_sources[0x6f]	75	1		T38	1		T163	1		T44	1
valid_sources[0x70]	62	1		T150	1		T162	2		T176	7
valid_sources[0x71]	63	1		T78	2		T150	1		T159	1
valid_sources[0x72]	55	1		T154	1		T44	1		T92	3
valid_sources[0x73]	144	1		T77	1		T44	3		T90	1
valid_sources[0x74]	116	1		T31	1		T153	2		T46	3
valid_sources[0x75]	55	1		T41	1		T42	1		T90	2
valid_sources[0x76]	90	1		T81	1		T161	1		T175	1
valid_sources[0x77]	78	1		T92	2		T94	2		T95	3
valid_sources[0x78]	74	1		T168	1		T46	3		T92	8
valid_sources[0x79]	76	1		T46	1		T92	4		T93	3
valid_sources[0x7a]	55	1		T44	2		T46	4		T95	5
valid_sources[0x7b]	63	1		T161	1		T153	1		T46	7
valid_sources[0x7c]	68	1		T92	2		T94	2		T103	1
valid_sources[0x7d]	71	1		T174	2		T41	2		T46	1
valid_sources[0x7e]	70	1		T163	1		T44	2		T41	1
valid_sources[0x7f]	65	1		T31	2		T44	2		T92	5
valid_sources[0x80]	83	1		T44	3		T46	1		T43	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6927

1

T44

62

T47

2

T41

12

values[0x0]

all_enables

biggest_size

6524

1

T29

3

T33

1

T31

4

values[0x1]

all_enables

biggest_size

6178

1

T30

2

T31

5

T80

1