Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	255752	1		T2	2		T4	1		T5	36
full_word	594687	1		T2	6		T4	2		T5	24

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	850099	1		T2	8		T4	3		T5	60
auto[TlIntgErrCmd]	127	1		T41	6		T42	8		T43	5
auto[TlIntgErrData]	96	1		T41	2		T42	3		T43	5
auto[TlIntgErrBoth]	117	1		T41	2		T42	9		T43	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	523492	1		T2	4		T5	12		T7	8
auto[1]	326947	1		T2	4		T4	3		T5	48

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrData]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	213222	1		T2	2		T5	10		T7	3
auto[TlIntgErrNone]	partial	auto[1]	42221	1		T4	1		T5	26		T7	1
auto[TlIntgErrNone]	full_word	auto[0]	310120	1		T2	2		T5	2		T7	5
auto[TlIntgErrNone]	full_word	auto[1]	284536	1		T2	4		T4	2		T5	22
auto[TlIntgErrCmd]	partial	auto[0]	49	1		T41	3		T42	1		T43	3
auto[TlIntgErrCmd]	partial	auto[1]	65	1		T41	3		T42	7		T43	1
auto[TlIntgErrCmd]	full_word	auto[0]	7	1		T133	1		T134	1		T135	2
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T43	1		T134	1		T136	1
auto[TlIntgErrData]	partial	auto[0]	40	1		T41	1		T43	4		T133	2
auto[TlIntgErrData]	partial	auto[1]	48	1		T41	1		T42	2		T43	1
auto[TlIntgErrData]	full_word	auto[0]	8	1		T42	1		T137	1		T138	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1		T42	4		T43	3		T133	1
auto[TlIntgErrBoth]	partial	auto[1]	67	1		T41	2		T42	5		T43	6
auto[TlIntgErrBoth]	full_word	auto[0]	6	1		T43	1		T133	1		T137	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T133	1		T139	1		T136	1