Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.03	90.91	61.70	87.88		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	47917814	12623	0	0
late_debug_enable_rd_A	47917814	3356	0	0
late_debug_enable_regwen_rd_A	47917814	4213	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47917814	12623	0	0
T41	20921	2	0	0
T42	99484	3	0	0
T43	85208	3	0	0
T44	6820	710	0	0
T71	736258	75	0	0
T72	322991	258	0	0
T84	5623	171	0	0
T85	9048	377	0	0
T86	8969	159	0	0
T87	161145	26	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47917814	3356	0	0
T42	99484	86	0	0
T45	5368	4	0	0
T46	246868	234	0	0
T71	736258	58	0	0
T87	161145	35	0	0
T88	76725	18	0	0
T90	46479	77	0	0
T92	402220	1025	0	0
T93	54571	29	0	0
T102	8811	5	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47917814	4213	0	0
T42	99484	98	0	0
T45	5368	5	0	0
T46	246868	209	0	0
T71	736258	55	0	0
T87	161145	25	0	0
T88	76725	10	0	0
T90	46479	38	0	0
T92	402220	1949	0	0
T93	54571	7	0	0
T126	6470	14	0	0