SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 169 | 169 | 0 | 0 |
OutputsKnown_A | 26834666 | 26777888 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26834666 | 26777888 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 169 | 169 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26834666 | 26777888 | 0 | 0 |
T1 | 199048 | 198970 | 0 | 0 |
T2 | 7989 | 7932 | 0 | 0 |
T3 | 112858 | 111934 | 0 | 0 |
T10 | 3687 | 3628 | 0 | 0 |
T12 | 228755 | 228142 | 0 | 0 |
T29 | 1061 | 998 | 0 | 0 |
T30 | 1675 | 1618 | 0 | 0 |
T32 | 223650 | 222776 | 0 | 0 |
T33 | 965 | 886 | 0 | 0 |
T48 | 23869 | 22884 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26834666 | 26777888 | 0 | 0 |
T1 | 199048 | 198970 | 0 | 0 |
T2 | 7989 | 7932 | 0 | 0 |
T3 | 112858 | 111934 | 0 | 0 |
T10 | 3687 | 3628 | 0 | 0 |
T12 | 228755 | 228142 | 0 | 0 |
T29 | 1061 | 998 | 0 | 0 |
T30 | 1675 | 1618 | 0 | 0 |
T32 | 223650 | 222776 | 0 | 0 |
T33 | 965 | 886 | 0 | 0 |
T48 | 23869 | 22884 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |