1f410ef5dc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 0 | 2 | 0.00 | ||
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0 | 20 | 0.00 | ||
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 0 | 20 | 0.00 | ||
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 0 | 2 | 0.00 | ||
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 0 | 2 | 0.00 | ||
| V1 | cmderr_exception | rv_dm_cmderr_exception | 0 | 2 | 0.00 | ||
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 0 | 2 | 0.00 | ||
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 0 | 2 | 0.00 | ||
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 0 | 2 | 0.00 | ||
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0 | 2 | 0.00 | ||
| V1 | halt_resume | rv_dm_halt_resume_whereto | 0 | 2 | 0.00 | ||
| V1 | progbuf_busy | rv_dm_progbuf_busy | 0 | 2 | 0.00 | ||
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 0 | 2 | 0.00 | ||
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 0 | 2 | 0.00 | ||
| V1 | progbuf_exception | rv_dm_cmderr_exception | 0 | 2 | 0.00 | ||
| V1 | rom_read_access | rv_dm_rom_read_access | 0 | 2 | 0.00 | ||
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | rv_dm_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | rv_dm_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 0 | 5 | 0.00 | ||
| rv_dm_csr_rw | 0 | 20 | 0.00 | ||||
| V1 | mem_walk | rv_dm_mem_walk | 0 | 5 | 0.00 | ||
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 0 | 161 | 0.00 | |||
| V2 | idcode | rv_dm_smoke | 0 | 2 | 0.00 | ||
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 0 | 2 | 0.00 | ||
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 0 | 2 | 0.00 | ||
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 0 | 2 | 0.00 | ||
| V2 | sba | rv_dm_sba_tl_access | 0 | 20 | 0.00 | ||
| rv_dm_delayed_resp_sba_tl_access | 0 | 20 | 0.00 | ||||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 0 | 20 | 0.00 | ||
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 0 | 20 | 0.00 | ||
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 0 | 2 | 0.00 | ||
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | rv_dm_ndmreset_req | 0 | 2 | 0.00 | ||
| V2 | hart_unavail | rv_dm_hart_unavail | 0 | 5 | 0.00 | ||
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 0 | 1 | 0.00 | ||
| rv_dm_tap_fsm_rand_reset | 0 | 40 | 0.00 | ||||
| V2 | stress_all | rv_dm_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | rv_dm_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 0 | 5 | 0.00 | ||
| rv_dm_csr_hw_reset | 0 | 5 | 0.00 | ||||
| rv_dm_csr_rw | 0 | 20 | 0.00 | ||||
| rv_dm_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 0 | 5 | 0.00 | ||
| rv_dm_csr_hw_reset | 0 | 5 | 0.00 | ||||
| rv_dm_csr_rw | 0 | 20 | 0.00 | ||||
| rv_dm_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 276 | 0.00 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 0 | 5 | 0.00 | ||
| rv_dm_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | sec_cm_lc_dft_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 512 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 28 | 28 | 0 | 0.00 |
| V2 | 18 | 16 | 0 | 0.00 |
| V2S | 10 | 2 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
User terminated with CTRL-C has 512 failures:
Test rv_dm_csr_aliasing has 5 failures.
0.rv_dm_csr_aliasing.32433892155049457996768574704370137298078846844617035200784675543311350347385
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest/run.log
1.rv_dm_csr_aliasing.12485655362800682020800984197533404787251975502423429746263213560625968626352
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest/run.log
... and 3 more failures.
Test rv_dm_smoke has 2 failures.
0.rv_dm_smoke.5502101451582863841252021373514320222797736816794519292751796344254006745959
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_smoke/latest/run.log
1.rv_dm_smoke.67757444408380365667933138996587420982167372550479519845461957690781080399009
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_smoke/latest/run.log
Test rv_dm_tap_fsm has 1 failures.
Test rv_dm_jtag_dtm_csr_hw_reset has 5 failures.
0.rv_dm_jtag_dtm_csr_hw_reset.82641058142568346053083470919725590099674203330786692133289014986028878184403
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log
1.rv_dm_jtag_dtm_csr_hw_reset.67273189415604368254420418887591695216884316772153465844625429651855409505851
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log
... and 3 more failures.
Test rv_dm_jtag_dtm_csr_rw has 20 failures.
0.rv_dm_jtag_dtm_csr_rw.110957572327739077745746389202790328077942796350706667569914830396829419155359
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest/run.log
1.rv_dm_jtag_dtm_csr_rw.7390946302353225932163253342113644946738535162790964481052674981011781238326
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest/run.log
... and 18 more failures.
... and 42 more tests.
Job killed most likely because its dependent job failed. has 2 failures:
cov_merge
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/cov_merge/merged.vdb/cov_merge.log
cov_report
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/cov_report/cov_report.log