Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 197231 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 528506 1 T7 1 T4 7 T5 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 465965 1 T30 80 T16 16 T31 8
values[0x0] 127784 1 T7 2 T4 20 T5 2
values[0x1] 131988 1 T7 3 T4 15 T5 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 150165 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 575572 1 T7 1 T4 10 T5 1



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2862 1 T36 1 T37 1 T40 8
valid_sources[0x01] 2978 1 T29 2 T73 4 T17 1
valid_sources[0x02] 2841 1 T6 1 T39 6 T40 13
valid_sources[0x03] 2970 1 T6 1 T66 4 T40 26
valid_sources[0x04] 3033 1 T134 2 T39 1 T66 3
valid_sources[0x05] 2990 1 T6 1 T18 1 T51 1
valid_sources[0x06] 2593 1 T6 1 T51 2 T39 5
valid_sources[0x07] 2579 1 T6 1 T37 5 T39 1
valid_sources[0x08] 2351 1 T6 1 T30 1 T31 1
valid_sources[0x09] 2906 1 T6 1 T30 1 T16 1
valid_sources[0x0a] 3329 1 T6 1 T17 1 T18 1
valid_sources[0x0b] 2649 1 T6 1 T52 1 T135 2
valid_sources[0x0c] 3018 1 T30 1 T39 4 T66 4
valid_sources[0x0d] 2958 1 T40 13 T67 1 T41 23
valid_sources[0x0e] 2609 1 T30 1 T17 1 T52 1
valid_sources[0x0f] 2685 1 T17 3 T40 14 T67 4
valid_sources[0x10] 2747 1 T30 1 T16 1 T39 1
valid_sources[0x11] 2688 1 T6 1 T40 21 T67 1
valid_sources[0x12] 3049 1 T39 1 T66 1 T40 16
valid_sources[0x13] 2707 1 T6 1 T16 1 T37 6
valid_sources[0x14] 2979 1 T16 1 T80 5 T37 6
valid_sources[0x15] 2752 1 T6 1 T30 1 T16 1
valid_sources[0x16] 9293 1 T18 1 T10 7 T66 7
valid_sources[0x17] 2496 1 T6 1 T37 1 T40 18
valid_sources[0x18] 2794 1 T16 1 T52 1 T54 1
valid_sources[0x19] 2603 1 T30 1 T18 1 T135 1
valid_sources[0x1a] 2347 1 T6 1 T51 1 T66 4
valid_sources[0x1b] 2954 1 T30 1 T66 1 T40 9
valid_sources[0x1c] 2399 1 T6 1 T18 1 T135 1
valid_sources[0x1d] 2663 1 T6 1 T30 1 T31 1
valid_sources[0x1e] 2482 1 T66 8 T40 15 T41 23
valid_sources[0x1f] 2772 1 T33 3 T134 1 T66 9
valid_sources[0x20] 2705 1 T4 2 T18 1 T66 2
valid_sources[0x21] 2685 1 T16 1 T51 1 T39 4
valid_sources[0x22] 2622 1 T12 3 T51 1 T37 4
valid_sources[0x23] 3009 1 T30 1 T39 1 T66 8
valid_sources[0x24] 3625 1 T16 1 T40 14 T67 1
valid_sources[0x25] 2957 1 T31 1 T66 3 T40 17
valid_sources[0x26] 3055 1 T6 1 T30 1 T18 1
valid_sources[0x27] 2680 1 T6 1 T30 1 T37 6
valid_sources[0x28] 2866 1 T30 2 T16 1 T18 1
valid_sources[0x29] 2695 1 T18 2 T51 2 T66 4
valid_sources[0x2a] 3039 1 T6 1 T30 1 T66 21
valid_sources[0x2b] 2122 1 T16 1 T51 2 T66 4
valid_sources[0x2c] 2776 1 T7 1 T6 1 T16 1
valid_sources[0x2d] 2195 1 T6 1 T17 1 T18 1
valid_sources[0x2e] 2652 1 T17 1 T18 1 T39 1
valid_sources[0x2f] 3196 1 T17 3 T18 2 T40 4
valid_sources[0x30] 3126 1 T4 2 T18 1 T52 1
valid_sources[0x31] 2757 1 T18 1 T39 3 T40 11
valid_sources[0x32] 2562 1 T17 4 T37 1 T39 5
valid_sources[0x33] 2561 1 T30 2 T18 2 T66 7
valid_sources[0x34] 3035 1 T6 1 T18 1 T36 2
valid_sources[0x35] 2387 1 T6 1 T17 2 T51 1
valid_sources[0x36] 3260 1 T6 1 T66 4 T40 7
valid_sources[0x37] 2647 1 T80 9 T134 1 T40 9
valid_sources[0x38] 2790 1 T17 3 T18 1 T52 2
valid_sources[0x39] 2481 1 T30 1 T18 1 T37 10
valid_sources[0x3a] 3415 1 T16 1 T80 1 T51 1
valid_sources[0x3b] 2617 1 T30 1 T40 12 T67 1
valid_sources[0x3c] 2553 1 T6 1 T30 1 T17 1
valid_sources[0x3d] 2770 1 T6 1 T16 1 T40 8
valid_sources[0x3e] 2890 1 T4 1 T17 3 T135 1
valid_sources[0x3f] 3249 1 T55 2 T135 2 T40 19
valid_sources[0x40] 2629 1 T16 1 T17 1 T40 9
valid_sources[0x41] 3107 1 T6 1 T29 1 T18 1
valid_sources[0x42] 2303 1 T6 1 T17 4 T80 8
valid_sources[0x43] 2686 1 T6 1 T40 12 T67 3
valid_sources[0x44] 2892 1 T51 1 T39 3 T66 6
valid_sources[0x45] 2972 1 T17 4 T66 1 T40 24
valid_sources[0x46] 2591 1 T17 5 T18 1 T39 1
valid_sources[0x47] 2622 1 T7 1 T30 1 T17 1
valid_sources[0x48] 2789 1 T17 3 T18 1 T66 1
valid_sources[0x49] 2501 1 T80 2 T66 4 T40 11
valid_sources[0x4a] 2521 1 T16 1 T53 2 T66 3
valid_sources[0x4b] 2702 1 T4 1 T30 2 T18 1
valid_sources[0x4c] 2958 1 T30 2 T16 1 T31 1
valid_sources[0x4d] 2437 1 T16 1 T136 98 T37 3
valid_sources[0x4e] 2876 1 T51 1 T40 17 T41 10
valid_sources[0x4f] 2682 1 T16 1 T18 1 T137 40
valid_sources[0x50] 3835 1 T6 1 T16 1 T10 2
valid_sources[0x51] 2568 1 T17 2 T18 2 T54 2
valid_sources[0x52] 2490 1 T6 1 T30 2 T29 1
valid_sources[0x53] 2530 1 T18 1 T52 2 T138 1
valid_sources[0x54] 3161 1 T30 1 T16 1 T31 1
valid_sources[0x55] 2316 1 T17 1 T18 1 T36 1
valid_sources[0x56] 2583 1 T17 2 T52 1 T56 1
valid_sources[0x57] 3153 1 T16 1 T10 1 T39 2
valid_sources[0x58] 2649 1 T17 7 T40 18 T41 36
valid_sources[0x59] 2405 1 T30 1 T134 1 T39 2
valid_sources[0x5a] 2848 1 T17 2 T18 1 T37 1
valid_sources[0x5b] 2382 1 T6 1 T66 6 T40 14
valid_sources[0x5c] 2622 1 T51 1 T10 1 T37 15
valid_sources[0x5d] 2514 1 T16 1 T18 1 T53 2
valid_sources[0x5e] 2708 1 T16 1 T18 1 T51 2
valid_sources[0x5f] 2363 1 T4 3 T6 1 T18 1
valid_sources[0x60] 2613 1 T24 1 T17 5 T39 2
valid_sources[0x61] 2776 1 T17 2 T37 3 T40 11
valid_sources[0x62] 3190 1 T6 1 T30 1 T17 1
valid_sources[0x63] 2571 1 T16 1 T17 4 T51 2
valid_sources[0x64] 2716 1 T29 2 T17 3 T37 6
valid_sources[0x65] 2941 1 T17 2 T40 17 T41 10
valid_sources[0x66] 2919 1 T16 1 T51 1 T66 2
valid_sources[0x67] 3089 1 T51 2 T134 1 T39 2
valid_sources[0x68] 2754 1 T18 2 T37 2 T39 1
valid_sources[0x69] 2689 1 T6 1 T16 1 T52 3
valid_sources[0x6a] 2308 1 T56 1 T37 8 T66 1
valid_sources[0x6b] 2725 1 T6 1 T30 1 T16 1
valid_sources[0x6c] 2997 1 T17 1 T50 2 T51 1
valid_sources[0x6d] 2547 1 T6 1 T12 7 T51 1
valid_sources[0x6e] 2227 1 T18 1 T33 1 T39 2
valid_sources[0x6f] 2529 1 T16 1 T17 8 T18 1
valid_sources[0x70] 3706 1 T80 1 T37 4 T40 14
valid_sources[0x71] 2319 1 T6 1 T16 1 T51 1
valid_sources[0x72] 3405 1 T4 7 T30 1 T19 4
valid_sources[0x73] 2566 1 T33 1 T53 1 T51 1
valid_sources[0x74] 2813 1 T18 2 T51 2 T37 3
valid_sources[0x75] 2693 1 T51 1 T135 1 T66 7
valid_sources[0x76] 3311 1 T40 9 T67 2 T41 41
valid_sources[0x77] 2814 1 T17 6 T37 2 T40 12
valid_sources[0x78] 2567 1 T18 1 T10 2 T40 8
valid_sources[0x79] 2659 1 T18 2 T39 3 T40 13
valid_sources[0x7a] 2892 1 T6 1 T37 4 T66 3
valid_sources[0x7b] 2212 1 T30 1 T40 9 T67 4
valid_sources[0x7c] 2195 1 T5 1 T6 1 T30 1
valid_sources[0x7d] 3367 1 T30 1 T18 2 T37 1
valid_sources[0x7e] 2586 1 T6 1 T17 3 T51 1
valid_sources[0x7f] 2705 1 T31 1 T80 8 T66 8
valid_sources[0x80] 3218 1 T4 2 T6 1 T40 4



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 276827 1 T30 80 T16 7 T31 3
values[0x0] all_enables biggest_size 126013 1 T7 1 T4 5 T5 1
values[0x1] all_enables biggest_size 125666 1 T4 2 T6 5 T16 8


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5015 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 17281 1 T1 6 T2 2 T28 3



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 9564 1 T36 23 T37 31 T39 72
values[0x0] 6179 1 T1 10 T2 6 T28 5
values[0x1] 6553 1 T1 10 T2 5 T28 6



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3868 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 18428 1 T1 6 T2 3 T28 5



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 194 1 T2 11 T139 1 T37 3
valid_sources[0x01] 69 1 T72 1 T140 1 T39 2
valid_sources[0x02] 285 1 T141 8 T36 1 T39 2
valid_sources[0x03] 106 1 T45 11 T142 1 T36 1
valid_sources[0x04] 49 1 T39 1 T68 3 T82 8
valid_sources[0x05] 53 1 T143 1 T144 1 T66 2
valid_sources[0x06] 79 1 T39 1 T66 3 T67 1
valid_sources[0x07] 75 1 T145 15 T39 7 T66 1
valid_sources[0x08] 84 1 T66 4 T67 1 T68 2
valid_sources[0x09] 117 1 T59 15 T36 1 T37 2
valid_sources[0x0a] 61 1 T36 1 T39 3 T66 4
valid_sources[0x0b] 40 1 T42 1 T72 1 T146 1
valid_sources[0x0c] 55 1 T36 1 T78 11 T122 1
valid_sources[0x0d] 71 1 T144 1 T66 2 T67 2
valid_sources[0x0e] 64 1 T42 1 T147 1 T148 1
valid_sources[0x0f] 112 1 T66 2 T40 2 T67 1
valid_sources[0x10] 45 1 T39 1 T66 2 T67 4
valid_sources[0x11] 138 1 T66 1 T67 5 T68 2
valid_sources[0x12] 59 1 T148 3 T39 1 T66 6
valid_sources[0x13] 86 1 T144 1 T39 2 T66 5
valid_sources[0x14] 93 1 T66 3 T40 2 T67 1
valid_sources[0x15] 191 1 T149 1 T36 1 T39 3
valid_sources[0x16] 74 1 T39 1 T66 1 T67 1
valid_sources[0x17] 65 1 T39 2 T66 3 T41 1
valid_sources[0x18] 67 1 T36 1 T39 1 T66 1
valid_sources[0x19] 83 1 T39 1 T66 2 T67 1
valid_sources[0x1a] 49 1 T150 1 T151 1 T66 2
valid_sources[0x1b] 78 1 T39 3 T66 3 T67 2
valid_sources[0x1c] 88 1 T39 1 T67 2 T75 1
valid_sources[0x1d] 91 1 T36 1 T39 1 T66 1
valid_sources[0x1e] 72 1 T152 22 T39 2 T66 1
valid_sources[0x1f] 163 1 T39 1 T66 9 T67 3
valid_sources[0x20] 130 1 T148 1 T39 3 T66 4
valid_sources[0x21] 38 1 T28 1 T151 1 T36 2
valid_sources[0x22] 84 1 T37 9 T66 1 T67 2
valid_sources[0x23] 86 1 T153 1 T148 1 T39 4
valid_sources[0x24] 41 1 T143 1 T66 2 T67 2
valid_sources[0x25] 65 1 T39 1 T66 2 T154 3
valid_sources[0x26] 75 1 T42 1 T36 1 T39 2
valid_sources[0x27] 58 1 T66 1 T67 3 T41 2
valid_sources[0x28] 62 1 T39 1 T66 3 T67 1
valid_sources[0x29] 34 1 T144 3 T66 2 T67 1
valid_sources[0x2a] 47 1 T39 3 T67 3 T76 1
valid_sources[0x2b] 38 1 T39 7 T67 1 T68 1
valid_sources[0x2c] 79 1 T39 3 T66 3 T67 1
valid_sources[0x2d] 69 1 T146 1 T36 2 T39 1
valid_sources[0x2e] 39 1 T39 2 T66 5 T68 2
valid_sources[0x2f] 92 1 T66 1 T67 1 T75 2
valid_sources[0x30] 43 1 T36 2 T75 1 T84 2
valid_sources[0x31] 76 1 T155 19 T37 1 T66 4
valid_sources[0x32] 36 1 T71 1 T66 1 T68 1
valid_sources[0x33] 74 1 T36 2 T39 1 T66 3
valid_sources[0x34] 68 1 T39 1 T66 1 T40 3
valid_sources[0x35] 46 1 T156 11 T37 1 T39 1
valid_sources[0x36] 65 1 T39 2 T66 1 T75 1
valid_sources[0x37] 47 1 T68 1 T76 1 T86 2
valid_sources[0x38] 70 1 T157 3 T158 1 T39 2
valid_sources[0x39] 61 1 T36 1 T66 1 T67 3
valid_sources[0x3a] 42 1 T148 1 T66 2 T67 2
valid_sources[0x3b] 60 1 T159 3 T39 4 T66 1
valid_sources[0x3c] 80 1 T157 2 T37 21 T67 2
valid_sources[0x3d] 65 1 T71 1 T66 6 T67 2
valid_sources[0x3e] 202 1 T39 1 T67 1 T81 3
valid_sources[0x3f] 86 1 T36 1 T39 3 T66 3
valid_sources[0x40] 227 1 T39 1 T66 5 T86 7
valid_sources[0x41] 64 1 T160 9 T36 1 T39 1
valid_sources[0x42] 49 1 T39 3 T66 3 T67 1
valid_sources[0x43] 40 1 T66 2 T67 3 T75 1
valid_sources[0x44] 59 1 T39 3 T66 2 T75 2
valid_sources[0x45] 93 1 T1 20 T66 1 T67 1
valid_sources[0x46] 56 1 T36 1 T39 5 T66 4
valid_sources[0x47] 283 1 T39 1 T66 2 T67 1
valid_sources[0x48] 59 1 T39 3 T66 4 T67 1
valid_sources[0x49] 60 1 T161 1 T39 2 T66 3
valid_sources[0x4a] 52 1 T71 2 T39 4 T66 3
valid_sources[0x4b] 84 1 T36 1 T39 1 T66 4
valid_sources[0x4c] 81 1 T162 5 T66 4 T68 1
valid_sources[0x4d] 53 1 T72 1 T66 1 T67 1
valid_sources[0x4e] 68 1 T36 1 T66 1 T67 5
valid_sources[0x4f] 73 1 T35 1 T150 2 T39 4
valid_sources[0x50] 128 1 T66 4 T68 1 T85 77
valid_sources[0x51] 80 1 T143 1 T139 1 T36 1
valid_sources[0x52] 99 1 T36 2 T66 3 T68 1
valid_sources[0x53] 96 1 T118 6 T119 4 T149 3
valid_sources[0x54] 71 1 T150 1 T148 1 T66 1
valid_sources[0x55] 32 1 T39 1 T66 1 T68 3
valid_sources[0x56] 113 1 T37 2 T67 2 T68 2
valid_sources[0x57] 73 1 T36 1 T39 2 T66 1
valid_sources[0x58] 293 1 T39 3 T67 1 T78 4
valid_sources[0x59] 57 1 T142 1 T66 2 T67 1
valid_sources[0x5a] 74 1 T36 1 T39 1 T66 4
valid_sources[0x5b] 58 1 T36 1 T39 3 T66 4
valid_sources[0x5c] 161 1 T158 1 T39 1 T66 1
valid_sources[0x5d] 41 1 T28 1 T143 1 T39 1
valid_sources[0x5e] 28 1 T67 2 T68 1 T83 1
valid_sources[0x5f] 43 1 T39 2 T66 8 T75 2
valid_sources[0x60] 54 1 T144 1 T39 2 T66 2
valid_sources[0x61] 267 1 T72 1 T67 1 T75 1
valid_sources[0x62] 244 1 T148 1 T161 1 T39 2
valid_sources[0x63] 44 1 T67 1 T38 2 T75 1
valid_sources[0x64] 54 1 T39 1 T66 1 T67 1
valid_sources[0x65] 213 1 T36 1 T39 1 T67 2
valid_sources[0x66] 176 1 T39 1 T66 1 T67 1
valid_sources[0x67] 66 1 T163 2 T151 1 T39 1
valid_sources[0x68] 82 1 T39 1 T66 2 T67 3
valid_sources[0x69] 50 1 T164 11 T144 1 T66 2
valid_sources[0x6a] 91 1 T163 1 T36 1 T39 1
valid_sources[0x6b] 127 1 T36 1 T39 1 T66 2
valid_sources[0x6c] 46 1 T42 1 T66 5 T67 1
valid_sources[0x6d] 87 1 T39 3 T66 5 T67 1
valid_sources[0x6e] 59 1 T39 1 T67 2 T86 10
valid_sources[0x6f] 48 1 T90 3 T39 1 T66 2
valid_sources[0x70] 69 1 T66 2 T67 1 T76 1
valid_sources[0x71] 812 1 T71 1 T139 1 T66 1
valid_sources[0x72] 55 1 T42 1 T39 5 T76 2
valid_sources[0x73] 57 1 T39 3 T66 2 T67 2
valid_sources[0x74] 47 1 T140 1 T39 1 T66 3
valid_sources[0x75] 56 1 T39 1 T66 2 T67 1
valid_sources[0x76] 219 1 T139 1 T161 1 T36 1
valid_sources[0x77] 93 1 T39 1 T75 1 T77 24
valid_sources[0x78] 93 1 T36 1 T66 2 T68 1
valid_sources[0x79] 35 1 T36 1 T39 4 T66 1
valid_sources[0x7a] 96 1 T142 2 T36 2 T66 2
valid_sources[0x7b] 55 1 T158 1 T39 5 T66 2
valid_sources[0x7c] 108 1 T72 1 T39 1 T66 3
valid_sources[0x7d] 135 1 T36 1 T39 1 T66 4
valid_sources[0x7e] 77 1 T66 2 T40 1 T67 3
valid_sources[0x7f] 196 1 T39 1 T66 6 T67 1
valid_sources[0x80] 44 1 T142 1 T144 1 T66 3



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 6436 1 T36 23 T37 29 T39 70
values[0x0] all_enables biggest_size 5450 1 T1 4 T2 1 T28 1
values[0x1] all_enables biggest_size 5395 1 T1 2 T2 1 T28 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%