Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	231872	1		T7	4		T4	28		T5	2
full_word	529831	1		T7	1		T4	7		T5	1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	761403	1		T7	5		T4	35		T5	3
auto[TlIntgErrCmd]	92	1		T76	10		T92	3		T122	8
auto[TlIntgErrData]	109	1		T76	4		T92	3		T122	4
auto[TlIntgErrBoth]	99	1		T76	6		T92	4		T122	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	467440	1		T30	80		T16	16		T31	8
auto[1]	294263	1		T7	5		T4	35		T5	3

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	190319	1		T16	9		T31	5		T17	29
auto[TlIntgErrNone]	partial	auto[1]	41277	1		T7	4		T4	28		T5	2
auto[TlIntgErrNone]	full_word	auto[0]	276973	1		T30	80		T16	7		T31	3
auto[TlIntgErrNone]	full_word	auto[1]	252834	1		T7	1		T4	7		T5	1
auto[TlIntgErrCmd]	partial	auto[0]	42	1		T76	6		T92	2		T122	3
auto[TlIntgErrCmd]	partial	auto[1]	42	1		T76	4		T122	4		T125	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T122	1		T129	1		T130	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T92	1		T126	1		T131	1
auto[TlIntgErrData]	partial	auto[0]	50	1		T76	3		T92	1		T122	2
auto[TlIntgErrData]	partial	auto[1]	50	1		T76	1		T92	2		T122	2
auto[TlIntgErrData]	full_word	auto[0]	6	1		T125	1		T126	1		T132	2
auto[TlIntgErrData]	full_word	auto[1]	3	1		T127	1		T133	2		-	-
auto[TlIntgErrBoth]	partial	auto[0]	42	1		T76	4		T92	2		T122	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T76	2		T92	2		T122	7
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T126	1		T127	1		T129	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T125	2		-	-		-	-